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| EM78P813 8-BIT OTP MICRO-CONTROLLER Version 1.6 ELAN MICROELECTRONICS CORP. No. 12, Innovation 1st RD., Science-Based Industrial Park Hsin Chu City, Taiwan, R.O.C. TEL: (03) 5639977 FAX: (03) 5630118 EM78P813 8-bit OTP Micro-controller Specification Revision History Version Content EM78813 ICE 1.0 Initial version 1.1 Add "VNWSB" pin Add touch panel pen press / unpress detection 1.2 Remove "VNWSB" pin Change FSK, DTMF and CW power control 1.3 Modify Current DA resolution from 7 bits to 10 bits 1.4 Add 208 pin QFP package 1.5 1. Modify normal mode operation voltage 2. Modify DC electrical characteristic 3. Remove AD and Touch panel function 1.6 Remove Idle mode EM78R813 EM78P813 16K X 8 16K X 8 64K X 13 64K X 13 256K X 8 256K X 8 2M X 8 2M X 8 32 24 256 byte 128 byte O X O O Share with TIP Independent pin Chipsel pin decide Chipsel pin decide 256 186 .5 .5 EM78813 4K X 8 48K X 13 256K X 8 -24 128 byte X O Independent pin Share with SEG 184 .5 2002/12/25 2003/3/4 2003/3/26 2003/9/1 2003/12/3 2004/8/19 EM78815 4K X 8 64K X 13 256K X 8 2M X 8 24 128 byte X O Independent pin Share with IO 105 .35 Data RAM PRG ROM DATA ROM Expand ROM STACK Common RAM OP Current DA DED input Key scan Pin Process EM78813/EM78815 mode select EM78813 mode(IOCB page1 bit6=0) KEY strobe pin Share with SEG50~SEG65 Internal LCD driver Enable Expand function NO EM78815 mode(IOCB page1 bit6=1) Share with PORT8 and PORT9 Disable(COM,SEG pin high impedance) Interface share with SEG34~SEG65 Application Note 1. 2.0V reference voltage will power down when both RD PAGE2 bit7(DAREF) and RA PAGE2 bit7(CMPEN) are clear to 0. 2. For targeting interrupt and program run to address 0x0008, ACC, R3(STATUS), R5(Program page) and R4(6,7) will be automatically saved and R3(6,7) R register page will set to PAGE0, and reload after the instruction "RETI". 3. Before using Key tone function, please set Port 76 as output type. 4. In EM78R813, pin EGIN1 and EGIN2 are shared with pin TIP and RIN, but they are independent in EM78P813 and EM78813. 5. In EM78R813, user can turn on one of FSK, DTMF and CW power at the same time. In OTP and mask version, user can turn on both CID(one of FSK and DRMF) or CW power at the same time, but FSK and DTMF power can not turn on simultaneously. 6. Please do not switch MCU operation mode from normal mode to sleep mode directly. Before into sleep mode, please switch MCU to green mode. 7.For accessing data ROM,EM78P813 (OTP) can work at 10.74MHz, but please note that ROM type EM78813 only can work at 5.37MHz 8. While switching main clock (regardless of high freq to low freq or on the other hand), adding 6 instructions delay (NOP) is required. __________________________________________________________________________________________________________________________________________________________________ * This specification is subject to change without notice. 2 2004/8/19 (V1.6) EM78P813 8-bit OTP Micro-controller I. General Description The EM78P813 is an 8-bit CID (Call Identification) RISC type microprocessor with low power, high speed CMOS technology. There are 64Kx13 bits and 256Kx8 bits Electrical One Time Programmable Read Only Memory (OTP-ROM) within it. It provides security bits and some One time programmable Option bits to protect the OTP memory code from any external access as well as to meet user's options. Integrated onto a single chip are on chip watchdog (WDT), programmable real time clock/counter, external/internal interrupt, power down mode, LCD driver, FSK decoder, Call waiting decoder, Energy Detector (DED) , DTMF receiver, Programming Tone generator, build-in KEY TONE clock generation, Comparator and tri-state I/O. The EM78P813 provides a single chip solution to design a CID of calling message display. II. Feature CPU E Operating voltage : 2.2V~5.5V at main CLK less then 3.58MHz. Main CLK(Hz) Under 3.58M 5.37M 10.74M Operating Voltage(min) 2.2 2.5 3 E 64KN 13 Program ROM E 256KN 8 data ROM E 16KN 8 data RAM E 128N 8 common register E Up to 56 bi-directional tri-state I/O ports (32 shared with LCD Segment pins) E IO with internal Pull high, wake-up and interrupt functions E STACK: 24 level stack for subroutine nesting E TCC: 8-bit real time clock/counter (TCC) with 8-bit prescaler E COUNTER1: 8 or 16 bit counter with 8-bit prescaler can be an interrupt source E COUNTER2: 8-bit counter with 8-bit prescaler can be an interrupt source E Watch Dog : Programmable free running on chip watchdog timer E CPU modes: Mode CPU status Main clock 32.768kHz clock status Sleep mode Turn off Turn off Turn off Green mode Turn on Turn off Turn on Normal mode Turn on Turn on Turn on E 4 step Normal mode CLK : 1.79 , 3.58 , 5.37 , 10.74 MHz generated by internal PLL. E 13 interrupt source , 8 external , 5 internal E Key Scan : Port key scan function up to 16x4 keys E Sub-Clock: 32.768KHz crystal. E Key tone output :4KHz, 2KHz ,1KHz (shared with IO) E Comparator: 3-channel comparators: internal (16 level) or external reference voltage. (shared with IO) Serial transmitter/receiver interface E Serial Peripheral Interface (SPI): Interrupt flag available for the read buffer full, Programmable baud rates of communication, Three-wire synchronous communication. (shared with IO) Current D/A E Operation Voltage : 2.5Va 5.5V E 10-bit resolution and 3-bit output level control E Current DA output can drive speaker through a transistor for sound playing. (shared with IO) Programmable Tone Generators E Operation Voltage 2.2Va 5.5V E Programmable Tone1 and Tone2 generators E Independent single tone generation for Tone1 and Tone2 __________________________________________________________________________________________________________________________________________________________________ * This specification is subject to change without notice. 3 2004/8/19 (V1.6) EM78P813 8-bit OTP Micro-controller E Mixed dual tone generation by Tone1 and Tone2 with 2dB difference E Can be programmed for DTMF tone generation E Can be programmed for FSK signal (Bell202 or V.23) generation CID E Operation Voltage 2.7Va 5.5V for FSK E Operation Voltage 2.7Va 5.5V for DTMF receiver E Compatible with Bellcore GR-30-CORE (formerly as TR-NWT-000030) E Compatible with British Telecom (BT) SIN227 & SIN242 E FSK demodulator for Bell 202 and ITU-T V.23 (formerly as CCITT V.23) E Differential Energy Detector (DED) for line energy detection CALL WAITING E Operation Voltage 2.6Va 5.5V E Compatible with Bellcore special report SR-TSV-002476 E Call-Waiting (2130Hz plus 2750Hz) Alert Signal Detector E Good talkdown and talkoff performance E Sensitivity compensated by adjusting input OP gain LCD (16x112 , 24x106 , 32x98 ) E Operating Voltage range: Supply voltage : 2.5V to 5.5V Through charge pump circuit and regulate adjusting, LCD device voltage : 3.6V to 5.3V E Maximum common driver pins : 16/24/32 E Maximum segment driver pins : 112(SEG0..SEG111)/106(SEG0..SEG105)/ 106(SEG0..SEG97) E Shared COM16 ~ COM23 pins with SEG113 ~ SEG106 pins E Shared COM24 ~ COM31 pins with SEG105 ~ SEG98 pins E 1/5 bias for 16 common mode , 1/6 bias for 24 common mode and 1/7 for 32 common mode E 1/16, 1/24, 1/32 duty E 32 Level LCD contrast control (software) E Internal resistor circuit for LCD bias. External LCD controller (64 x 256 dot MAX for a pair of Master and Slave LCD Driver) E Multi-chip operation(Master, Slave) available for external LCD device. Expand E 128K Program ROM (64K on_chip and provided Parallel transmitter interface for 64K external program ROM access.)Through external address & data bus, 2M byte Data ROM can be addressing. Package type E 186 pin die : EM78P813H E 208 pin QFP : EM78P813AQ(POVD disable) EM78P813BQ(POVD enable) III. Application E adjunct units E SMS phones E feature phones __________________________________________________________________________________________________________________________________________________________________ * This specification is subject to change without notice. 4 2004/8/19 (V1.6) EM78P813 8-bit OTP Micro-controller IV. Pin Configuration SEG49/EXA5 SEG48/EXA6 SEG47/EXA7 SEG46/EXA8 SEG45/EXA9 SEG44/EXA10 SEG43/EXA11 SEG42/EXA12 SEG41/EXA13 SEG40/EXA14 SEG39/EXA15 SEG38/EXA16 SEG37/EXA17 SEG36/EXA18 SEG35/EXA19 SEG34/EXA20 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 SEG50/EXA4 SEG51/EXA3 SEG52/EXA2 SEG53/EXA1 SEG54/EXA0 SEG55/CS SEG56/WR SEG57/RD SEG58/EXD7 SEG59/EXD6 SEG60/EXD5 SEG61/EXD4 SEG62/EXD3 SEG63/EXD2 SEG64/EXD1 SEG65/EXD0 LVDD VC5 VC4 VC3 VC2 VC1 VREF C2 C1 Vout LVSS SEG66/P80 SEG67/P81 SEG68/P82 SEG69/P83 SEG70/P84 SEG71/P85 SEG72/P86 SEG73/P87 SEG74/P90 SEG75/P91 SEG76P92 SEG77/P93 SEG78/P94 SEG79/P95 SEG80/P96 SEG81/P97 SEG82/PB0/LD0 SEG83/PB1/LD1 __________________________________________________________________________________________________________________________________________________________________ * This specification is subject to change without notice. 5 VDD VDD XIN XOUT /RESET P70/INT0 P71/INT1 P72/INT2 P73/INT3 P74/INT4 P75/INT5 P76/INT6/KTONE P77/INT7 EXSEL CHIPSEL TEST GND COM16 COM17 COM18/SEG111 COM19/SEG110 COM20/SEG109 COM21/SEG108 COM22/SEG107 COM23/SEG106 COM24/SEG105 COM25/SEG104 COM26/SEG103 COM27/SEG102 COM28/SEG101 COM29/SEG100 COM30/SEG99 COM31/SEG98 SEG97/PC7 SEG96/PC6 SEG95/PC5 SEG94/PC4/A0 SEG93/PC3/RD SEG92/PC2/WR SEG91/PC1/CS1 SEG90/PC0/CS2 SEG89/PB7/LD7 SEG88/PB6/LD6 SEG87/PB5/LD5 SEG86/PB4/LD4 SEG85/PB3/LD3 SEG84/PB2/LD2 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 SEG0 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 AVDD POVD PLLC TONE TIP RING CWGS CWIN EGIN1 EGIN2 POVD AVSS P60/STGT P61/EST P62 P63 P64 P65/CMP1 P66CMP2 P67CMP3 PD0 PD1 PD2 PD3 PD4/SCK PD5/SDO PD6/SDI PD7/DAOUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 Fig.1_a : EM78P813 die pin assignment 2004/8/19 (V1.6) EM78P813 8-bit OTP Micro-controller SEG42/EXA12 SEG41/EXA13 SEG40/EXA14 SEG39/EXA15 SEG38/EXA16 SEG37/EXA17 SEG36/EXA18 SEG35/EXA19 SEG34/EXA20 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 NC NC NC NC NC NC NC NC NC NC 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 SEG43/EXA11 SEG44/EXA10 SEG45/EXA9 SEG46/EXA8 SEG47/EXA7 SEG48/EXA6 SEG49/EXA5 SEG50/EXA4 SEG51/EXA3 SEG52/EXA2 SEG53/EXA1 SEG54/EXA0 SEG55/CS SEG56/WR SEG57/RD SEG58/EXD7 SEG59/EXD6 SEG60/EXD5 SEG61/EXD4 SEG62/EXD3 SEG63/EXD2 SEG64/EXD1 SEG65/EXD0 LVDD VC5 VC4 NC NC NC VC3 VC2 VC1 VREF C2 C1 Vout LVSS SEG66/P80 SEG67/P81 SEG68/P82 SEG69/P83 SEG70/P84 SEG71/P85 SEG72/P86 SEG73/P87 SEG74/P90 SEG75/P91 SEG76P92 SEG77/P93 SEG78/P94 SEG79/P95 SEG80/P96 SEG0 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 AVDD PLLC TONE TIP RING CWGS CWIN EGIN1 EGIN2 AVSS P60/STGT P61/EST P62 P63 P64 P65/CMP1 P66/CMP2 P67/CMP3 PD0 PD1 PD2 PD3 PD4/SCK PD5/SDO PD6/SDI PD7/DAOUT VDD XIN XOUT /RESET P70/INT0 NC NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 __________________________________________________________________________________________________________________________________________________________________ * This specification is subject to change without notice. 6 NC NC NC NC NC NC NC NC P71/INT1 P72/INT2 P73/INT3 P74/INT4 P75/INT5 P76/INT6/KTONE P77/INT7 EXSEL CHIPSEL TEST GND COM16 COM17 COM18/SEG111 COM19/SEG110 COM20/SEG109 COM21/SEG108 COM22/SEG107 COM23/SEG106 COM24/SEG105 COM25/SEG104 COM26/SEG103 COM27/SEG102 COM28/SEG101 COM29/SEG100 COM30/SEG99 COM31/SEG98 SEG97/PC7 SEG96/PC6 SEG95/PC5 SEG94/PC4/A0 SEG93/PC3/RD SEG92/PC2/WR SEG91/PC1/CS1 SEG90/PC0/CS2 SEG89/PB7/LD7 SEG88/PB6/LD6 SEG87/PB5/LD5 SEG86/PB4/LD4 SEG85/PB3/LD3 SEG84/PB2/LD2 SEG83/PB1/LD1 SEG82/PB0/LD0 SEG81/P97 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 Fig.1_b : EM78P813 208 pin QFP pin assignment 2004/8/19 (V1.6) EM78P813 8-bit OTP Micro-controller V. Functional Block Diagram VDD AVDD DTMF signal FSK signal DTMF Receiver MCU FSK Decoder CW Decoder Dual Tone Generator Program ROM DATA RAM PLL DATA ROM LCD RAM Voltage Regulator 2.7 V X2 Charge Pump V1~V5 Generator & driving ability control LCD driver Energy Detector Current DA CAS TONE Analog input Comparator COM&SEG Data Serial IO (SPI/UART) VSS AVSS FSK DTMF CAS signal DAOUT Fig.2 Xin Xout PLLC W DT timer Oscillator timing control R1(TCC) Control sleep and wake-up on I/O port GENERAL RAM R4 prescalar Block diagram1 ROM R2 STACK Interruption control Instruction register R3 R5 ALU ACC Instruction decoder DATA & CONTROL BUS LCD RAM DATA RAM DATA ROM FSK DECODER FSK DECODER Call waiting decoder DTM F receiver DTM F receiver DUAL TONE GENERATOR DUAL TONE GENERATOR KEY TONE KEY TONE SERIAL I/O SERIAL I/O COM PARATOR COM PARATOR CURRENT DA Energy Detector PORT6 IOC6 R6 PORT7 IOC7 R7 PORT8 IOC8 R8 PORT9 IOC9 R9 PORTB IOCB RB PORTC IOCC RC PORTD IOCD RD P60~P67 P70~P77 P80~P87 P90~P97 PB0~PB7 PC0~PC7 PD0~PD2 Fig.3 Block diagram2 __________________________________________________________________________________________________________________________________________________________________ * This specification is subject to change without notice. 7 2004/8/19 (V1.6) EM78P813 8-bit OTP Micro-controller VI. Pin Descriptions I. POWER pin Pin VDD AVDD LVDD GND AVSS LVSS II. CLOCK pin Pin XIN XOUT PLLC I/O POWER POWER POWER POWER POWER POWER I/O I O I Description Digital Power Analog Power Charge pump used power Digital Ground Analog Ground Charge pump used power Description Input pin for 32.768 kHz oscillator Output pin for 32.768 kHz oscillator Phase loop lock capacitor, connect a capacitor 0.01u to 0.047u with GND III.1. Embedded LCD pin Pin COM0..COM15 COM16..COM23 COM24..COM31 SEG0..SEG65 SEG66..SEG73 SEG74..SEG81 SEG82..SEG89 SEG90..SEG97 C1,C2 Vout VREF VC1..VC5 Description Common driver pins of LCD drivers COM16..COM23 are shared with SEG111..SEG106 COM24..COM31 are shared with SEG105..SEG98 Segment driver pins of LCD drivers Segment driver pins of LCD drivers share with PORT8 Segment driver pins of LCD drivers share with PORT9 Segment driver pins of LCD drivers share with PORTB Segment driver pins of LCD drivers share with PORTC Charge Pump capacitor. C1 connect 1uF Cap To C2. Charge pump output voltage ,connect 1uF Cap to GND 2.7V, need to be connected 0.1uF capacitor to GND Reference voltage input. Each one connect a capacitor (0.1u) with GND. III.2. External LCD device control pin Pin I/O Description LCDD0..LCDD7 I/O External LCD driver data bus. Shared with PORTB0..PORTB7. /WR O Write enable output (active low signal). Shared with PORTC2. /RD O Read enable output (active low signal). Shared with PORTC3. A0 O Used as register selection. When A0 equal to 1, data bus transmit LCD DATA. When A0 equal to 0,data bus transmit LCD Address. The pin shared with PORTC4. /CS1../CS2 O Chip Selection signal output. Shared with PORTC1..PORTC0 IV. FSK,CW Pin I/O Description TIP I Should be connected with TIP side of twisted pair lines for FSK. RING I Should be connected with RING side of twisted pair lines for FSK. CWGS O Gain adjustment of single-ended input OP Amp CWIN I Single-ended input OP Amp for call waiting decoder EGIN1,EGIN2 I DED input V. DTMF receiver Pin I/O Description EST O Early steering output. Presents a logic high immediately when __________________________________________________________________________________________________________________________________________________________________ I/O O O O O O O O O I * This specification is subject to change without notice. 8 2004/8/19 (V1.6) EM78P813 8-bit OTP Micro-controller the digital algorithm detects a recognizable tone-pair (signal condition). Any momentary loss of signal condition will cause EST to return to a logic low. This pin shared with PORT61. STGT I/O Steering input/guard time output (bi-directional). A voltage greater than Vtst detected at ST causes the device to register the detected tone-pair and update the output latch. A voltage less than Vtst frees the device to accept a new tone-pair. The GT output acts to reset the external steering time-constant; its state is a function of EST and the voltage on ST . This pin shared with PORT60. VI. Serial IO, Comparator , Current DA , Tone Pin I/O Description SCK I/O Master: output pin , Slave: input pin. This pin shared with PORTD4 SDO O Output pin for serial data transferring. This pin shared with PORTD5. SDI I Input pin for receiving data. This pin shared with PORTD6. CMP1 I Comparator input pins. Shared with PORT65. CMP2 I Comparator input pins. Shared with PORT66 CMP3 I Comparator input pins. Shared with PORT67. DAOUT O Current DA output pin. It can be a control signal for sound generating. Shared with PORTD7. KTONE O Key tone output. Shared with PORT76. TONE O Dual tone output pin VII. IO Pin I/O Description P60 ~P67 I/O PORT 6 can be INPUT or OUTPUT port each bit. Internal pull high. P70 ~ P77 I/O PORT 7 can be INPUT or OUTPUT port each bit. Internal Pull high function. Auto key scan function. Interrupt function. Shared with Key tone output P80 ~ P87 I/O PORT 8 can be INPUT or OUTPUT port each bit. Shared with LCD Segment signal. P90 ~ P97 I/O PORT 9 can be INPUT or OUTPUT port each bit. Shared with LCD Segment signal. PB0 ~ PB7 I/O PORT B can be INPUT or OUTPUT port each bit. Shared with LCD Segment signal. PC0 ~ PC7 I/O PORT C can be INPUT or OUTPUT port each bit. Shared with LCD Segment signal. PD0 ~ PD7 I/O PORT D can be INPUT or OUTPUT port each bit. Shared with SPI pin Share with CMP input pin. P70 ~ P76 I Interrupt sources. Any pin from PORT70 to PORT76 has a falling edge signal, it will generate a corresponding interruption.. P77 I Interrupt source. Once PORT77 has a falling edge or rising edge signal (controlled by CONT register), it will generate a interruption. /RESET I Low reset __________________________________________________________________________________________________________________________________________________________________ * This specification is subject to change without notice. 9 2004/8/19 (V1.6) EM78P813 8-bit OTP Micro-controller VIII Expand Program/Data ROM interface Pin I/O Description EXD0 ~ EXD7 I/O Expand Program/Data memory Data Bus RD O Expand Program/Data memory Read request output WR O Expand Program/Data memory Write request output CS O Expand Program/Data memory CS request output EXA-1~EXA19 O Expand Program/Data memory Address Bus EXSEL I 0/1 Internal 64K Program ROM select used/unused CHIPSEL Pin : EM78813 or EM78815 function select . In EM78813 mode , Key strobe pin are share with SEG50 ~ SEG 65. If select to EM78815 mode , Key strobe pin are share with I/O Port8 and Port9. SEG34 ~SEG65 pin will switch to expand flash memory interface. Connect to ground EM78813 mode Connect to VDD EM78815 mode EM78813 mode COM2 V1 V2 V4 V5 GND SEG V1 V2 V4 V5 GND V1 V2 V4 V5 30us GND Fig.4(a) : EM78813 mode Key scan signal(share with SEG pin) __________________________________________________________________________________________________________________________________________________________________ * This specification is subject to change without notice. 10 2004/8/19 (V1.6) EM78815 mode (must set RE page2 bit2 ~ bit4 = 1) Key scan pin(P8,P9) VDD 30us GND Fig.4(b) : EM78815 mode Key scan signal(share with IO pin) EXSEL pin : 0/1 On-Chip program ROM used/unused switch(EM78815 mode only). EM78P813 support MAX 128K Program . User can port program to both 64K EM78P813 on_chip ROM and 64K expand ROM . User also can ignore 64K EM78P813 on_chip ROM and porting all programs to a external 128K ROM. Using this function, user can upgrade program or download new function easily. EM78P813 provide Data ROM expand function. When user access data which address is over 256K, external ROM will be load. User must set expand start address of Data ROM to RF PAGE1, PAGE2 and IOCB PAGE1. A diagram of expand function is as below. MAX 2M Byte Expand ROM (FLASH ROM) Expand Data ROM start address 64K Program ROM (PAGE0 ~ PAGE 63) RF PAGE2 64K word Program ROM (PAGE64~PAGE127) IOCB B7 b7 b0 b7 RF PAGE1 b0 0 0 0 XXXX XXXXXXXXXXXXX0 ROM Address 17 ROM Address 9 ROM Address 0 256K byte Data ROM ExpandData ROM EM78P813 (EXSEL pin go low) Fig5(a) : EXSEL = 0,both internal and external program are used. EM78P813 8-bit OTP Micro-controller MAX 2M Byte Expand ROM (FLASH ROM) Expand Data ROM start address 64K Program ROM Unused RF PAGE2 128K word Program ROM (PAGE0~PAGE127) IOCB B7 b7 b0 b7 RF PAGE1 b0 0 0 0 XXXX XXXXXXXXXXXXX0 ROM Address 17 ROM Address 9 ROM Address 0 256K byte Data ROM ExpandData ROM EM78P813 (EXSEL pin pull high) Fig5(b) : EXSEL = 1, only external program are used. How to set start address for expanding Data ROM? EM78815 support maximum 2M Byte expanding data memory, but user must fix the start address of external program at 0x00000 and set start address of expanding Data ROM by user. By this way, MCU will get data from external memory if the data ROM is over 256K. The width of an instruction is 13 bit and the data bus for external memory is 8bit, so an instruction will captured two address size and the LSB address of start address at external ROM will be 0. Besides, EM78815 only support MAX 128K program, so the start address of Data ROM will smaller than 256K-2 andA20, A19 and A18 will be 0 also. User only has to according to write Data ROM address A17~A1 to IOCB PAGE2 bi7,RF PAGE3 and RF PAGE2. EM78P813 writer pin OTP writer PIN NAME 1.VDD 2.VPP 3.DINCK 4.ACLK 5.PGM 6.OE 7.DATA 8.GND 9.ROMSEL MASK ROM PIN NAME VDD,AVDD /RESET P77 P76 P75 P74 P73 VSS,AVSS,TEST P72 P.S. High : Data ROM Low : Program ROM __________________________________________________________________________________________________________________________________________________________________ * This specification is subject to change without notice. 12 2004/8/19 (V1.6) EM78P813 8-bit OTP Micro-controller VII. Function Descriptions VII.1 Operational Register REGISTER PAGE0 Address REGISTER PAGE1 REGISTER PAGE2 REGISTER PAGE3 Control REGISTER PAGE0 Control REGISTER PAGE1 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 : 1F R4 P1(7,8) P3(7) R1(TCC Buffer) R2(PC) R1(Real Interrupt flag1) R1(Real Interrupt flag2) R1(UART receiver buffer) R3(6,7) R3(STATUS) R4(RSR,bank select) R5(Program page) R6(Port6 IO data) R7(Port7 IO data) R8(Port8 IO data) R9(Port9 IO data) RA(Power saving , FSK) RB(PortB IO data) RC(PortC IO data) RD(PortD IO data) RE(Interrupt flag1) RF(Interrupt flag2) R4(Unused) R5(Counter setting) R6(DROM data buffer) R7(DROM address) R8(DROM address) R9(DROM address , LCD address MSB ) RA(LCD address) RB(LCD data buffer) RC(DRAM1 data buffer) RD(DRAM1 address) RE(DRAM1 address , DED output) RF(External Data ROM Start address LOW) R4(Undefined) R5(CNT1 low 8 bit data) R6(CNT1 high 8 bit data) R7(CNT2 data) R8(DTMF receiver) R9(CMP IO control) RA(Comparator control) RB(Key strobe control) RC(Key strobe control) RD(LCD control) RE(LCD control , Key scan , CAS) RF(External Data ROM Start address HIGH) R4(Undefined) R5( CurrentDA control) R6(CurrentDA control) R7(SPI control) R8(SPI data buffer) R9(Key tone control) RA(Tont1 control) RB(Tone2 control) RC(Undefined) RD(Undefined) RE(Undefined) RF(Undefined) R3(5) IOC5(Address auto inc/dec control) IOC6(Port6 I/O control) IOC7(Port7 I/O control) IOC8(Port8 I/O control) IOC9(Port9 I/O control) IOCA(STACK point) IOCB(PortB I/O control) IOCC(PortC I/O control) IOCD(PortD I/O control) IOCE(Interrupt mask1) IOCE(Interrupt mask2) IOC5(DRAM2 data buffer) IOC6(DRAM2 address) IOC7(DRAM2 address) IOC8(IO/SEG switch) IOC9(PB I/O/SEG switch) IOCA(PC I/O/SEG switch) IOCB(External LCD driver control interface) IOCC(P6 pull high control) IOCD(P7 pull high control) IOCE(DED control) 16 Byte Commom register DATA ROM R7 PAGE1 : address(L) R8 PAGE1 : address(M) R9 PAGE1 : address(H) R6 PAGE1 : data 20 : 3F LCD RAM RA PAGE1 : address Bank0 32x8 Bank1 32x8 Bank2 32x8 Bank3 32x8 RB PAGE1 : data DATA RAM(index1) RD PAGE1 : address(L) RE PAGE1 : address(H) RC PAGE1 : data DATA RAM(index2) IOC6 PAGE1 : address(L) IOC7 PAGE1 : address(H) IOC5 PAGE1 : data Commom register Fig.6: control register configuration VII.2 Operational Register Detail Description R0 Indirect Addressing Register R0 is not a physically implemented register. It is useful as indirect addressing pointer. Any instruction using R0 as register actually accesses data pointed by the RAM Select Register (R4). Example: Mov A , @0x20 ;store a address at R4 for indirect addressing Mov 0x04 , A Mov A , @0xAA ;write data 0xAA to R20 at bank0 through R0 Mov 0x00 , A R1 PAGE0 TCC data buffer TCC data buffer. Increased by 16.38KHz or by the instruction cycle clock (controlled by CONT register).Written and read by the program as any other register. __________________________________________________________________________________________________________________________________________________________________ * This specification is subject to change without notice. 13 2004/8/19 (V1.6) EM78P813 8-bit OTP Micro-controller R1 PAGE1 Interrupt Flag1 real value 7 6 5 4 INTR7 INTR6 INTR5 INTR4 3 INTR3 2 INTR2 1 INTR1 0 INTR0 Bit 0~Bit 7(INTR0~INTR7) : Interrupt flag1 real value. The relation of R1 Page1, RE PAGE0 and IOCE PAGE0 is shown in fig. When user disable interrupt mask, whether interrupt occur or not , interrupt flag(RE PAGE0) will appear "0". Opposite of RE PAGE0, R1 PAGE1 will show real interrupt occur status regardless this interrupt mask enable or disable. User can clear corresponding external interrupt flag by RE PAGE0 or R1 PAGE1. Interrupt Mask IOCE,IOCF Interrupt occur Interrupt Flag(RE,RF) Real Interrupt Flag(R0 P1,P2) Fig7 : Relation with interrupt mask ,flag and real flag R1 PAGE2 Interrupt Flag2 real value 7 6 5 RBF/STD FSK/CW X R/W-0 R/W-0 R/W-0 4 X R/W-0 3 DED R/W-0 2 CNT2 R/W-0 1 CNT1 R/W-0 0 TCC R/W-0 Bit 0~Bit 3, Bit 6~Bit 7(Internal interrupt flag real value) : Interrupt flag1 real value. The relation of R1 Page2, RF PAGE0 and IOCF PAGE0 is shown in fig7. When user disable interrupt mask, whether interrupt occur or not , interrupt flag(RF PAGE0) will appear "0". Opposite of RF PAGE0, R1 PAGE1 will show real interrupt occur status regardless this interrupt mask enable or disable. User can clear corresponding interrupt flag in RF PAGE0 or R1 PAGE2. Bit 4~ Bit 5 : Undefined register, these two bits are not allowed to use. R1 PAGE3 Undefined Register R1 page3 is undefined register, this is not allowed to use. External 128K x 13 PROGRAM ROM addresses to the relative programming instruction codes. The structure is depicted in Fig.8 "JMP" instruction allows the direct loading of the low 10 program counter bits. "CALL" instruction loads the low 10 bits of the PC, PC+1, and then push into the stack. "RET'' ("RETL k", "RETI") instruction loads the program counter with the contents at the top of stack. "MOV R2,A" allows the loading of an address from the A register to the PC, and the ninth and tenth bits are cleared to "0''. "ADD R2,A" allows a relative address be added to the current PC, and contents of the ninth and tenth bits are cleared to "0''. "TBL" allows a relative address be added to the current PC, and contents of the ninth and tenth bits don't change. The most significant bit (A10~A14) will be loaded with the content of bit PS0~PS3 in the status register (R5) upon the execution of a "JMP'', "CALL'', "ADD R2,A'', or "MOV R2,A'' instruction. If a interrupt trigger, PROGRAM ROM will jump to address 8 at page0. The CPU will store ACC,R3 status and R5 PAGE automatically, it will restore after instruction RETI. R2 Program Counter __________________________________________________________________________________________________________________________________________________________________ * This specification is subject to change without notice. 14 2004/8/19 (V1.6) EM78P813 8-bit OTP Micro-controller R5(PAGE) CALL and INTERRUPT A16 A15 A14 A13 A12 A11 A10 A9 A8 A7~A0 RET RETL RETI STACK1 STACK2 STACK3 STACK4 STACK5 STACK6 STACK7 STACK8 : : STACK30 STACK31 STACK32 1111110 PAGE126 1F800~1FBFF 1111111 PAGE127 1FC00~1FFFF 0000000 PAGE0 00000~003FF 0000001 PAGE1 00400~007FF 0000010 PAGE2 00800~00BFF store ACC,R3,R5(PAGE) restore Fig.8 : Program counter organization R3 Status Register 7 6 RS1 RS0 5 IOCS 4 T 3 P 2 Z 1 DC 0 C Bit 0 (C) : Carry Bit 1 (DC) : Auxiliary carry flag Bit 2 (Z) : Zero flag Bit 3 (P) : Power down bit. Set to 1 during power on or by a "WDTC" command and reset to 0 by a "SLEP" command. Bit 4 (T) : Time-out bit. Set to 1 by the "SLEP" and "WDTC" command, or during power up and reset to 0 by WDT timeout. EVENT WDT wake up from sleep mode WDT time out (not sleep mode) /RESET wake up from sleep Power up Low pulse on /RESET T 0 0 1 1 x P 0 1 0 1 X x : don't care REMARK Bit 5 (IOCS) : IOC register select bit. Change IOC5 ~ IOCE to another PAGE Bit 6~Bir 7 (RS0 ~ RS1) : R register select bits. Change R5 ~ RE to another PAGE. RS1 0 0 1 1 RS0 0 1 0 1 R PAGE PAGE 0 PAGE 1 PAGE 2 PAGE 3 __________________________________________________________________________________________________________________________________________________________________ * This specification is subject to change without notice. 15 2004/8/19 (V1.6) EM78P813 8-bit OTP Micro-controller R4 RAM select for common Registers R20~R3F , UART control PAGE0 7 6 5 4 3 2 RBS1 RBS0 RSR5 RSR4 RSR3 RSR2 1 RSR1 0 RSR0 Bit 0 ~ Bit 5 (RSR0 ~ RSR5) : Indirect addressing for common registers R20 ~ R3F RSR bits are used to select up to 32 registers (R20 to R3F) in the indirect addressing mode. Bit 6 ~ Bit 7 (RB0 ~ RB1) : Bank selection bits for common registers R20 ~ R3F These selection bits are used to determine which bank is activated among the 4 banks (RBS2 is in R4 PAGE3 Bit7) for 32 register (R20 to R3F).. R4 PAGE1 Undefined Register R4 page1 is undefined register, this is not allowed to use. PAGE2 Undefined Register 7 6 X X R/W-0 R/W-0 5 X R/W-0 4 X R/W-0 3 X R/W-0 2 X R/W-0 1 0 R/W-0 0 0 R/W-0 Bit 0 ~ Bit 1 : Undefined registers, please clear these two bits to 0. Bit 2 ~ Bit 7 : Undefined registers, these bits are not allowed to use. R4 PAGE3 Undefined Register R4 page3 is undefined register, this is not allowed to use. R5 Program page selection , CNT CLK & scale setting , CNT1 data(L) PAGE0 Program page 7 6 5 4 3 2 X PS6 PS5 PS4 PS3 PS2 X R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Bit 0 ~ Bit 6 (PS0 ~ PS6) : Program page selection bits 1 PS1 R/W-0 0 PS0 R/W-0 PS4 PS3 PS2 PS1 PS0 Program memory page (Address) 0 0 0 0 0 Page 0 0 0 0 0 1 Page 1 0 0 0 1 0 Page 2 0 0 0 1 1 Page 3 : : : : :: : : : : :: 1 1 1 1 1 1 0 Page 126 1 1 1 1 1 1 1 Page 127 User can use PAGE instruction to change page to maintain program page by user. Bit 7 : Unused. PS6 0 0 0 0 PS5 0 0 0 0 PAGE1 Counter1 Counter2 CLK and scale setting 7 6 5 4 3 CNT2S C2P2 C2P1 C2P0 CNT1S Bit 0~Bit 2(C1P0~C1P2) : Counter1 scaling 2 C1P2 1 C1P1 0 C1P0 __________________________________________________________________________________________________________________________________________________________________ * This specification is subject to change without notice. 16 2004/8/19 (V1.6) EM78P813 8-bit OTP Micro-controller C1P2 C1P1 C1P0 COUNTER1 0 0 0 1:2 0 0 1 1:4 0 1 0 1:8 0 1 1 1:16 1 0 0 1:32 1 0 1 1:64 1 1 0 1:128 1 1 1 1:256 Bit 3 (CNT1S) : Counter1 clock source 0/1 16.384kHz/instruction clock Bit 4~Bit 6(C2P0~C2P2) : Counter2 scaling. Prescaler is as different as Bit 0~Bit 2. C2P2 C2P1 C2P0 COUNTER2 0 0 0 1:2 0 0 1 1:4 0 1 0 1:8 0 1 1 1:16 1 0 0 1:32 1 0 1 1:64 1 1 0 1:128 1 1 1 1:256 Bit 7 (CNT2S) : Counter2 clock source 0/1 16.384kHz/instruction clock PAGE2 Counter 1 Low 8bit Data buffer 7 6 5 4 CN17 CN16 CN15 CN14 3 CN13 2 CN12 1 CN11 0 CN10 Bit 0~Bit 7(CN10~CN17) : Counter1's data buffer User can switch Counter1 between 8 bits or 16 bits counter by setting Control register bit 4. When CNT1BS set to 0, counter1 is a 8 bits up-counter with 8-bit prescaler that user can use R5 page2 to preset and read the counter. ( write = preset). Else counter1 will be a 16 bits up-counter with 8-bit prescaler and user can read or write the counter through R5 page2 and R6 page2. After a interruption, it will reload the preset value. Example: write: MOV 0x05,A ; write the data at accumulator to counter1 (preset) Example: read: MOV A,0x05 ; read R5 data and write to accumulator Example: write: MOV 0x06,A ; write the data(high 8 bits) at accumulator to counter1 Example: read: MOV A,0x06 ; read R6 data(high 8 bits) and write to accumulator PAGE3 Current DA Control 7 6 X X R-X R-X 5 X R-X 4 X R-X 3 CDAS R/W-0 2 CDAL2 R/W-0 1 CDAL1 R/W-0 0 CDAL0 R/W-0 Bit 0 ~ Bit 2 (DAL0 ~ DAL2) : change output level of current DA CDAL2 CDAL1 CDAL0 Output level 0 0 0 L0 (ratio = 1/8) 0 0 1 L1 (ratio = 2/8) 0 1 0 L2 (ratio = 3/8) 0 1 1 L3 (ratio = 4/8) 1 0 0 L4 (ratio = 5/8) 1 0 1 L5 (ratio = 6/8) 1 1 0 L6 (ratio = 7/8) 1 1 1 L7 (ratio =1) __________________________________________________________________________________________________________________________________________________________________ * This specification is subject to change without notice. 17 2004/8/19 (V1.6) EM78P813 8-bit OTP Micro-controller Bit 3 (CDAS) : Current DA switch 0 normal PORTD7 1 Current DA output Bit 4 ~ Bit 7 : These 4 bits are undefined, they are not allowed to use. R6 Port 6 I/O Data , Data ROM data buffer,CNT1 Data(H),DA control PAGE0 Port 6 I/O Data 7 6 5 4 3 2 P67 P66 P65 P64 P63 P62 R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X Bit 0 ~ Bit 7 (P60 ~ P67) : 8-bit PORT6 (0~7) I/O data register User can use IOC register to define input or output each bit.. 1 P61 R/W-X 0 P60 R/W-X PAGE1 Data ROM Data buffer 7 6 5 DRD7 DRD6 DRD5 R/W-X R/W-X R/W-X 4 DRD4 R/W-X 3 DRD3 R/W-X 2 DRD2 R/W-X 1 DRD1 R/W-X 0 DRD0 R/W-X Bit 0 ~ Bit 7 (DRD0 ~ DRD7) : Data ROM data buffer for ROM reading. Example. MOV A,@1 MOV R7_PAGE1,A MOV A,@0 MOV R8_PAGE1,A MOV A,@0 MOV R9_PAGE1,A MOV A,R6_PAGE1 ;read the data at Data ROM which address is "00001". PAGE2 Counter1 high 8bit Data buffer 7 6 5 4 CN1F CN1E CN1D CN1C 3 CN1B 2 CN1A 1 CN19 0 CN18 Bit 0~Bit 7(CN18~CN1F) : Counter1's high 8 bits data buffer. Please refer to IOC9 page2 counter1 low 8 bit data buffer for detail. PAGE3 DA Control 7 6 DA9 DA8 R/W-0 R/W-0 5 DA7 R/W-0 4 DA6 R/W-0 3 DA5 R/W-0 2 DA4 R/W-0 1 DA3 R/W-0 0 DA2 R/W-0 Bit 0 ~ Bit 7 (DA2 ~ DA9) : Current DA most significant 8 bits of Current DA output buffer Combine these 8 bits and R9 page3 bit4~bit5 2 bits as complete 10 bits Current DA output data. Control register bit3 is Current DA power control . __________________________________________________________________________________________________________________________________________________________________ * This specification is subject to change without notice. 18 2004/8/19 (V1.6) EM78P813 8-bit OTP Micro-controller VDD DA9..DA0 current DA circuit DAOUT PORTD7 PORTD7 M UX DAEN DAS Fig.12 Current DA structure R7 Port 7 I/O Data , Data ROM address , CNT2 Data , SPI control PAGE0 Port 7 I/O Data 7 6 5 4 3 2 P77 P76 P75 P74 P73 P72 R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X Bit 0 ~ Bit 7 (P70 ~ P77) : 8-bit PORT7(0~7) I/O data register User can use IOC register to define input or output each bit. 1 P71 R/W-X 0 P70 R/W-X PAGE1 Data ROM address 7 6 5 DRA7 DRA6 DRA5 R/W-X R/W-X R/W-X PAGE2 Counter2 Data buffer 7 6 5 CN27 CN26 CN25 R/W-0 R/W-0 R/W-0 4 DRA4 R/W-X 3 DRA3 R/W-X 2 DRA2 R/W-X 1 DRA1 R/W-X 0 DRA0 R/W-X Bit 0 ~ Bit 7 (DRA0 ~ DRA7) : Data ROM address ( 0~7 ) for ROM reading 4 CN24 R/W-0 3 CN23 R/W-0 2 CN22 R/W-0 1 CN21 R/W-0 0 CN20 R/W-0 Bit 0~Bit 7(CN20~CN27) : Counter2's data buffer User can read and write this buffer. Counter2 is a eight bit up-counter with 8-bit prescaler that user can use R7 page2 to preset and read the counter. ( write = preset) After a interruption, it will reload the preset value. Example: write: MOV 0x07 , A ; write the data at accumulator to counter1 (preset) Example: read: MOV A , 0x07 ; read R7 data and write to accumulator PAGE3 SPI Control Register 7 6 5 RBF SPIE SRO 4 SE 3 SCES 2 SBR2 1 SBR1 0 SBR0 Fig.7 shows how SPI to communicate with other device by SPI module. If SPI is a master controller, it sends clock through the SCK pin. An 8-bit data is transmitted and received at the same time. If SPI, however, is defined as a slave, its SCK pin could be programmed as an input pin. Data will continue to be shifted on a basis of both the clock rate and the selected edge. __________________________________________________________________________________________________________________________________________________________________ * This specification is subject to change without notice. 19 2004/8/19 (V1.6) EM78P813 8-bit OTP Micro-controller SDO SDI Master Device R5 page1 SPIR register SPIW register Salve Device SPIS Reg Bit7 Bit 0 SDI SDO SPI module SCK SCK Fig.13 Single SPI Master / Salve Communication Bit 0 ~ Bit 2 (SBR0 ~ SBR2) : SPI baud rate selection bits SBR2 SBR1 SBR0 Mode Baud rate 0 0 0 Master Fsco 0 0 1 Master Fsco/2 0 1 0 Master Fsco/4 0 1 1 Master Fsco/8 1 0 0 Master Fsco/16 1 0 1 Master Fsco/32 1 1 0 Slave 1 1 1 X __________________________________________________________________________________________________________________________________________________________________ * This specification is subject to change without notice. 20 2004/8/19 (V1.6) EM78P813 8-bit OTP Micro-controller Read R5 RBF RBFI SPIWC Write R5 SPIR reg. SPIW reg. set to 1 SPIE Buffer Full Detector SDI SDI/P62 MUX SPIS reg. PORT62 bit 0 SDO shift right bit 7 SDO/P61 SPIC reg. (R4 page1) MUX PORT61 Edge Select SPIE 0 3 SBR0 ~SBR2 SBR2~SBR0 3 2 Noise Filter Clock Select Tsco 16.38kHz Prescaler 4, 8, 16, 32, 64, 128 Edge Select SCK PORT60 M UX SCK/P60 SCK SPIE Fig.14 SPI Structure SPIC reg. : SPI control register SDO/P61 : Serial data out SDI/P62 : Serial data in SCK/P60 : Serial clock RBF : Set by buffer full detector, and reset in software. RBFI : Interrupt flag. Set by buffer full detector, and reset in software. Buffer Full Detector : Sets to 1, while an 8-bit shifting is complete. SE : Loads the data in SPIW register, and begin to shift SPIE : SPI control register SPIS reg. : Shifting byte out and in. The MSB will be shifted first. Both the SPIS register and the SPIW register are loaded at the same time. Once data being written to, SPIS starts transmission / reception. The received data will be moved to the SPIR register, as the shifting of the 8-bit data is complete. The RBF (Read Buffer Full ) flag and the RBFI(Read Buffer Full Interrupt) flag are set. SPIR reg. : Read buffer. The buffer will be updated as the 8-bit shifting is complete. The data must be read before the next reception is finished. The RBF flag is cleared as the SPIR register read. SPIW reg. : Write buffer. The buffer will deny any write until the 8-bit shifting is complete. The SE bit will be kept in 1 if the communication is still under going. This flag must be cleared as the shifting is finished. Users can determine if the next write attempt is available. SBR2 ~ SBR0: Programming the clock frequency/rates and sources. Clock select : Selecting either the internal instruction clock or the external 16.338KHz clock as the shifting clock. Edge Select : Selecting the appropriate clock edges by programming the SCES bit __________________________________________________________________________________________________________________________________________________________________ * This specification is subject to change without notice. 21 2004/8/19 (V1.6) EM78P813 8-bit OTP Micro-controller SCK (SCES=0) SCK (SCES=1) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SDO SDI RBF Shift data in Shift data out Clear by software Fig.15 SPI timing R8 Port 8 I/O Data , Data ROM address , DTMF receiver , SPI Data PAGE0 Port 8 I/O Data 7 6 5 4 3 2 P87 P86 P85 P84 P83 P82 Bit 0 ~ Bit 7 (P80 ~ P87) : 8-bit PORT8 ( 0~7 ) I/O data register User can use IOC register to define input or output each bit. 1 P81 0 P80 PAGE1 Data ROM address 7 6 5 DRA15 DRA14 DRA13 PAGE2 DTMF Receive 7 6 CMPFLAG STD 4 DRA12 3 DRA11 2 DRA10 1 DRA9 0 DRA8 Bit 0 ~ Bit 7 (DRA8 ~ DRA15) : Data ROM address ( 8~15 ) for ROM reading 5 - 4 - 3 Q4 2 Q3 1 Q2 0 Q1 Bit 0 ~ Bit 3 (Q1 ~ Q4) : DTMF receiver decoding data To provide the code corresponding to the last valid tone-pair received (see code table). STD signal which steering output presents a logic high when a received tone-pair has been registered and the Q4 ~ Q1 output latch updated and generate a interruption (IOCF has enabled); returns to logic low when the voltage on ST/GT falls below Vtst. F low F high Key DREN Q4~Q1 697 1209 1 1 0001 697 1336 2 1 0010 697 1477 3 1 0011 __________________________________________________________________________________________________________________________________________________________________ * This specification is subject to change without notice. 22 2004/8/19 (V1.6) EM78P813 8-bit OTP Micro-controller 770 770 770 852 852 852 941 941 941 697 770 852 941 Any 1209 1336 1477 1209 1336 1477 1209 1336 1477 1633 1633 1633 1633 Any 4 5 6 7 8 9 0 * # A B C D Any 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000 xxxx (x:unknown) Bit 4~Bit 5 : Unused Bit 6 (STD) : Delayed steering output. Presents a logic high when a received tone-pair has been registered and the output latch updated; returns to logic low when the voltage on St/GT falls below V tst. 0/1 Data invalid/data valid Be sure open main clock before using DTMF receiver circuit . A logic"0,0" applied to R5 page3 b4 and b3 will shut down power of the device to minimize the power consumption in a standby mode. It stops functions of the filters. In many situations not requiring independent selection of receive and pause, the simple steering circuit of is applicable. Component values are chosen according to the following formulae: t REC = t DP + t GTP t ID = t DA + t GTA The value of t DP is a parameter of the device and t REC is the minimum signal duration to be recognized by the receiver. A value for C of 0.1 uF is recommended for most applications, leaving R to be selected by the designer. For example, a suitable value of R for a t REC of 30mS would be 300k. Different steering arrangements may be used to select independently the guard-times for tone-present (t GTP ) and tone-absent (t GTA ). This may be necessary to meet system specifications which place both accept and reject limits on both tone duration and inter digital pause. Guard-time adjustment also allows the designer to tailor system parameters such as talk off and noise immunity. Increasing t REC improves talk-off performance, since it reduces the probability that tones simulated by speech will maintain signal condition for long enough to be registered. On the other hand, a relatively short t REC with a long t DO would be appropriate for extremely noisy environments where fast acquisition time and immunity to drop-outs would be required. VDD VDD C ST/GT EST R Fig.16 DTMF receiver delay time control __________________________________________________________________________________________________________________________________________________________________ * This specification is subject to change without notice. 23 2004/8/19 (V1.6) EM78P813 8-bit OTP Micro-controller TONE Tdp 5~20mS by S/W Tgtp 30mS Typ. ST/GT TONE Tgta 30mS Typ. EST Vtst 1/2 VDD Tpq 8 uS Typ. Q4..Q1 STD LINE_ENG Fig.17 DTMF receiver timing. Bit 7 (CMPFLAG) : Comparator output flag 0 Input voltage < reference voltage 1 Input voltage > reference voltage PAGE3 SPI Data buffer 7 6 SPIB7 SPIB6 5 SPIB5 4 SPIB4 3 SPIB3 2 SPIB2 1 SPIB1 0 SPIB0 Bit 0 ~ Bit 7 (SPIB0 ~ SPIB7) : SPI data buffer If you write data to this register, the data will write to SPIW register. If you read this data, it will read the data from SPIR register. Please refer to Fig.9 R9 Port 9 I/O Data , LCD address MSB , Data ROM address ,OP , Key tone control, PAGE0 Port 9 I/O Data 7 6 5 4 3 2 1 0 P97 P96 P95 P94 P93 P92 P91 P90 Bit 0 ~ Bit 7 (P90 ~ P97) : 8-bit PORT9 ( 0~7 ) I/O data register User can use IOC register to define input or output each bit. PAGE1 LCD address MSB , Data ROM address 7 6 5 4 3 LCDA8 DRA20 DRA19 2 DRA18 1 DRA17 0 DRA16 Bit 0 ~ Bit 4 (DRA16 ~ DRA20) : Data ROM address(16~20) for ROM reading.. Bit 5~Bit 6 : Unused Bit 7 (LCDA8) : MSB of LCD address for internal LCD RAM reading or writing Other LCD address bits LCDA7 ~ LCDA0 are set from RA PAGE1 Bit 7 ~ Bit 0. For LCD address access over 0xFFH, set this bit to "1"; otherwise set this bit to "0". __________________________________________________________________________________________________________________________________________________________________ * This specification is subject to change without notice. 24 2004/8/19 (V1.6) EM78P813 8-bit OTP Micro-controller PAGE2 OP input control Register, FSK/CW/DTMF Power select 7 6 5 4 3 2 PCTRL1 PCTRL0 ADCS3 ADCS2 ADCS1 Bit 0 ~ Bit 2 : Unused. Bit 3 ~ Bit 5(ADCS1 ~ ADCS3) : PORT65 ~ PORT67 normal IO or CMP input control bit. ADCSX = 1 Comparator input ADCSX = 0 normal IO Bit 6~Bit 7 (PCTRL0~PCTRL1) : FSK,CW and DTMF receiver power control bits PCTRL1 PCTRL0 Select Relation Register 0 0 FSK and DTMFr power off 0 1 FSK power on RA PAGE0 1 0 DTMF receiver power on R8 PAGE2 1 1 Can not used *Please do not set 1 to both the bits, or FSK and DTMFr function will fail.. *When User turn on DTMF receiver power, PORT60 and PORT61 will switch to /STGT and EST pin. 1 - 0 - PAGE3 KEY Tone Control 7 6 URT8 URR8 5 DA1 4 DA0 3 URINV 2 KT1 1 KT0 0 KTS Bit 0 (KTS) : Key tone output switch 0 normal PORT76 1 key tone output . Bit 1 ~ Bit 2 (KT0 ~ KT1) : Key tone output frequency and its power control KT1 KT0 Key tone frequency and power 0 0 32.768KHz/32 = 1.024kHz clock and enable 0 1 32.768KHz/16 = 2.048kHz clock and enable 1 0 32.768KHz/8 = 4.096kHz clock and enable 1 1 Power off key tone Bit 3(URINV) : Enable UART TXD, RXD port inverse output 0 Disable UART TXD, RXD port inverse output 1 Enable UART TXD, RXD port inverse output Bit 4 ~ Bit 5(DA0~DA1) :These two bits are the least significant 2 bits of Current DA. Combine R6 PAGE3 and these 2 bits as complete 10 bits Current DA output data. Bit 6(URR8) : MSB of UART receiver data buffer. Bit 7(URT8) : MSB of UART transmitter data buffer. RA CPU Power saving , main CLK select , FSK , WDT timer , LCD address Comparator control , Tone1 generator PAGE0 Power saving , main CLK select , FSK , WDT timer 7 6 5 4 3 2 1 PLLEN CLK1 CLK0 ROMRI FSKDATA /CD 0 0 WDTEN Bit 0 (WDTEN) : Watch dog control register User can use WDTC instruction to clear watch dog counter. The counter 's clock source is 32768/2 Hz. If the prescaler assigns to TCC. Watch dog will time out by (1/32768 )*2 * 256 = 15.616ms. If the prescaler assigns to WDT, the time of time out will be more times depending on the ratio of prescaler. 0/1 disable/enable __________________________________________________________________________________________________________________________________________________________________ * This specification is subject to change without notice. 25 2004/8/19 (V1.6) EM78P813 8-bit OTP Micro-controller Bit 1 (/CD) : FSK carrier detect indication 0/1 Carrier Valid/Carrier Invalid It's a read only signal. If FSK decoder detect the energy of mark or space signal. The Carrier signal will go to low level. Otherwise it will go to high.. Note!! Should be at normal mode. Bit 2 (FSKDATA) : FSK decoding data output It's a read only signal. If FSK decode the mark or space signal , it will output high level signal or low level signal at this register. It's a raw data type. That means the decoder just decode the signal and has no process on FSK signal. Note!! Should be at normal mode. User can use FSK data falling edge interrupt function to help data decoding. Example: MOV A,@01000000 IOW IOCF ;enable FSK interrupt function CLR RF ENI ;wait for FSK data's falling edge : 0 = Space data ( 2200Hz ) 1 = Mark data (1200Hz) FSK block power is controlled by R5 page3 bit3,4. When PCTRI1=0 and PCTRL0=1 , FSK power on. The relation between R5 bit3 to bit4 and RA bit1 to bit 2 are show in Fig.14. You have to power FSK decoder up first, then wait a setup time (Tsup) and check carrier signal (/CD). If the carrier is low, program can process the FSK data. FIRST RING 2 SECONDS TIP/RING SECOND RING 2 SECONDS 0.5 SEC FSK signal Tcdl 0.5 SEC Tcdh /CD Tdoc FSKDATA DATA Tsup PCTRL0 PCTRL1 Fig.18 The relation between R5 bit3 to bit4 and RA bit1 to bit 2 The controller is a CMOS device designed to support the Caller Number Deliver feature which is offered by the Regional Bell Operating Companies. The FSK block comprises one path: the signal path. The signal path consist of an input differential buffer, a band pass filter, an FSK demodulator and a data valid with carrier detect circuit. In a typical application, user can use his own external ring detect output as a triggering input to IO port. User can use this signal to wake up whole chip by external ring detect signal. By setting "0,1" to R5 b4 and b3 (PCTRL1 & PCTRL0) of register RA to activate the block of FSK decoder. If b4 and b3 of register R5 is set to "0,1", the block of FSK decoder will be powered down. The input buffer accepts a differential AC coupled input signal through the TIP and RING input and feeds this signal to a band pass filter. Once the signal is filtered, the FSK demodulator decodes the information and sends it to a post filter. The output data is then made available at bit 2 (FSKDATA) of register RA. This data, as sent by the central office, includes the header information (alternate "1" and "0") and 150 ms of marking which precedes the date, time and calling number. If __________________________________________________________________________________________________________________________________________________________________ * This specification is subject to change without notice. 26 2004/8/19 (V1.6) EM78P813 8-bit OTP Micro-controller no data is present, the bit 2 (DATA) of register RA is held on "1" state. This is accomplished by an carrier detect circuit which determines if the in-band energy is high enough. If the incoming signal is valid, bit 1 (/CD) of register RA will be "0" otherwise it will be held on "1". And thus the demodulated data is transferred to bit 2 (DATA) of register RA. If it is not, then the FSK demodulator is blocked. Bit 3 (ROMRI) : External Data ROM read data address auto_increase enable. RO_IDEN 0 1 1 ROMRI X 0 1 Result Regardless Read/Write external Data ROM, Address flag cannot increase or decrease. Address flag will auto_increase or decrease after Read/Write external Data ROM Address flag will auto_increase or decrease after Write external Data ROM, but address flag is constant after read external Data ROM. Bit 4 ~ Bit 5 (CLK0 ~ CLK1) : Main clock selection bits User can choose different frequency of main clock by CLK1 and CLK2. All the clock selection is list below. PLLEN 1 1 1 1 0 0 0 0 CLK1 0 0 1 1 Don't care Don't care Don't care Don't care CLK0 0 1 0 1 don't care don't care don't care don't care Sub clock 32.768kHz 32.768kHz 32.768kHz 32.768kHz 32.768kHz 32.768kHz 32.768kHz 32.768kHz MAIN clock 5.374MHz 1.7913MHz CPU clock 5.374MHz (Normal mode) 1.7913MHz (Normal mode) 10.7479MHz 10.7479MHz (Normal mode) 3.5826MHz Don't care Don't care Don't care Don't care 3.5826MHz (Normal mode) 32.768kHz (Green mode) 32.768kHz (Green mode) 32.768kHz (Green mode) 32.768kHz (Green mode) Bit 6 (PLLEN) : PLL enable control bit It is CPU mode control register. If PLL is enabled, CPU will operate at normal mode (high frequency , main clock); otherwise, it will run at green mode (low frequency, 32768 Hz). 0/1 disable/enable 3.5826M Hz to analog circuit PLL / 2 =>1.7913MHz x 1 =>3.5826MHz x 1.5 =>5.374M Hz x 3 =>10.7479M Hz 1 switch System clock 0 Sub-clock 32.768kHz ENPLL CLK1 ~ CLK0 Fig.19 The relation between 32.768kHz and PLL __________________________________________________________________________________________________________________________________________________________________ * This specification is subject to change without notice. 27 2004/8/19 (V1.6) EM78P813 8-bit OTP Micro-controller Bit 7: Unused register. Always keep this bit to 0 or some un-expect error will happen! The status after wake-up and the wake-up sources list as the table below. Wakeup signal SLEEP mode RA(7,6)=(0,0) + SLEP No function GREEN mode RA(7,6)=(x,0) no SLEP Interrupt (jump to address 8 at page0) NORMAL mode RA(7,6)=(x,1) no SLEP Interrupt (jump to address 8 at page0) Interrupt (jump to address 8 at page0) Interrupt (jump to address 8 at page0) RESET and Jump to address 0 Interrupt (jump to address 8 at page0) TCC time out IOCF bit 0=1 And "ENI" COUNTER1 time out IOCF bit 1=1 And "ENI" COUNTER2 time out IOCF bit 2=1 And "ENI" WDT time out PORT7 Any one bit in IOCE page0 = 1 And "ENI" Interrupt (jump to address 8 at page0) No function Interrupt (jump to address 8 at page0) RESET and RESET and Jump Jump to address to address 0 0 RESET and Interrupt Jump to address (jump to address 8 0 at page0) No function DED interrupt No function Interrupt Interrupt IOCE page1 bit 6 = 1 (jump to address 8 (jump to address And RF bit3 logic level at page0) 8 at page0) variation (switch by EDGE bit) And "ENI" Stack overflow No function Interrupt Interrupt IOC5 page1 bit7=1 (jump to address 8 (jump to address & RF bit 4: 0 1 at page0) 8 at page0) And "ENI" PAGE1 LCD address 7 6 LCDA7 LCDA6 5 LCDA5 4 LCDA4 3 LCDA3 2 LCDA2 1 LCDA1 0 LCDA0 Bit 0 ~ Bit 7 (LCDA0 ~ LCDA7) : LCD address for internal LCD RAM reading or writing The data in the internal LCD RAM correspond to the COMMON and SEGMENT signals as the table . COM31 ~ COM24 COM23 ~ COM16 COM15 ~COM8 COM7 ~ COM0 (set R9 PAGE1 (set R9 PAGE1 (set R9 PAGE1 (set R9 PAGE1 bit7=1) bit7=1) bit7=0) bit7=0) Address 180H Address 100H Address 080H Address 000H SEG0 Address 181H Address 101H Address 081H Address 001H SEG1 Address 182H Address 102H Address 082H Address 002H SEG2 : : : : : : : : : : __________________________________________________________________________________________________________________________________________________________________ * This specification is subject to change without notice. 28 2004/8/19 (V1.6) EM78P813 8-bit OTP Micro-controller : Address 1EEH Address 1EFH Address 1F0H : Address 1FFH : Address 16EH Address 16FH Address 170H : Address 17FH : Address 0EEH Address 0EFH Address 0F0H : Address 0FFH : Address 06EH Address 06FH Address 070H : Address 07FH : SEG110 SEG111 Empty : Empty PAGE2 Comparator control Register 7 6 5 4 CMPEN CMPREF CMPS1 CMPS0 3 CMPB3 2 CMPB2 1 CMPB1 0 CMPB0 If user define PORT63 , PORT64 or PORT65 (by CMPIN1, CMPIN2, CMPIN3 at R9 page2) as a comparator input or PORT6. User can use this register to control comparator's function. Bit 0~Bit 3(CMPB0 ~ CMPB3) : Reference voltage selection of internal bias circuit for comparator. Reference voltage for comparator = VDD x ( N + 0.5 )/ 16 , N = 0 to 15 Bit 4~Bit 5(CMPS0~CMPS1) : Channel selection from CMP1 to CMP3 for comparator CMPS1 CMPS0 Input 0 0 CMP1 0 1 CMP2 1 0 CMP3 1 1 Reserved Bit 6(CMPREF) : Switch for comparator reference voltage type 0 internal reference voltage 1 external reference voltage Bit 7(CMPEN) : Enable control bit of comparator. 0/1 disable/enable, When CMPEN bit set to "0" , 2.0V ref circuit will powered off. The relation between these registers shown in Fig.20. __________________________________________________________________________________________________________________________________________________________________ * This specification is subject to change without notice. 29 2004/8/19 (V1.6) EM78P813 8-bit OTP Micro-controller CMP1 M UX PORT65 P65/CM P1 ADCS1 P66/CM P2 M UX CM P2 M UX PORT66 ADCS2 P67/CMP3 CM P3 M UX PORT67 2 CMPS1 CMPS0 1 0 M UX + CM PFLAG ADCS3 VDD V2_0 ref. M UX 2.0V VR CMPREF CM PEN 1/2R 1111 R 1110 R MUX CM PEN VRSEL 0000 1/2R 4 CM PB3 to CMPB0 Fig.20 Comparator circuit CMPEN CMP1 to CMP3 reference voltage Setup time 10us CPU clock CMPFLAG Compare start Compare end Fig.21 Comparator timing PAGE3 Tone 1 Control Register 7 6 5 T17 T16 T15 Bit 0~Bit 7(T10~T17) : Tone generator1 frequency divider and power control Please Run in Normal mode . 4 T14 3 T13 2 T12 1 T11 0 T10 __________________________________________________________________________________________________________________________________________________________________ * This specification is subject to change without notice. 30 2004/8/19 (V1.6) EM78P813 8-bit OTP Micro-controller Clock source = 85300Hz T17~T10 = `11111111' Tone generator1 will has 334(85300/255) Hz SIN wave output. : : T17~T10 = `00000010' Tone generator1 will has 41150(85300/2) Hz SIN wave output. T17~T10 = `00000001' DC bias voltage output T17~T10 = `00000000' Power off Built-in tone generator can generate dialing tone signals for telephone of dialing tone type or just a single tone. In DTMF application, there are two kinds of tone. One is the group of row frequency (TONE1), the other is the group of column frequency (TONE2), each group has 4 kinds of frequency, user can get 16 kinds of DTMF frequency totally. Tone generator contains a row frequency sine wave generator for generating the DTMF signal which selected by RA page3 and a column frequency sine wave generator for generating the DTMF signal which selected by RB page3. This block can generate single tone by filling one of these two register. If all the values are low, the power of tone generators will turn off . TONE2 (RB page3) High group freq. 1201.4Hz 1332.8Hz 1470.7Hz 1640.4Hz (0X47) (0X40) (0X3A) (0X34) 699.2Hz(0x07A) 1 2 3 A 768.5Hz(0x06F) 4 5 6 B 853.0Hz(0x064) 7 8 9 C 937.4Hz(0x05B) * 0 # D TONE1(RA page3) Low group freq. Also TONE1 and TONE2 are an asynchronous tone generator so the both can be used to generate Caller ID FSK signal. In FSK generator application, TONE1 or TONE2 can generate 1200Hz Mark bit and 2200Hz Space bit for Bell202 or 1300Hz Mark bit and 2100Hz Space bit for V.23. See the following table. TONE1(IOCC PAGE1) or TONE2(IOCD PAGE1) 0x47 0x27 0x42 0x29 Freq. (Hz) 1201.4 2187.2 1292.4 2080.5 meaning Bell202 FSK Mark bit Bell202 FSK Space bit V.23 FSK Mark bit V.23 FSK Space bit Tone generator can also generate CW or SMS signal. See the following table. TONE1(IOCC PAGE1) or TONE2(IOCD PAGE1) 0x28 0x1F Freq. (Hz) 2132.5 2751.6 meaning CAS freq CAS freq RB Port B I/O Data , LCD Data buffer , Key strobe , Tone 2 generator PAGE0 Port B I/O Data 7 6 5 4 3 2 PB7 PB6 PB5 PB4 PB3 PB2 Bit 0 ~ Bit 7 (PB0 ~ PB7) : 8-bit PORTB ( 0~7 ) I/O data register User can use IOC register to define input or output each bit. 1 PB1 0 PB0 __________________________________________________________________________________________________________________________________________________________________ * This specification is subject to change without notice. 31 2004/8/19 (V1.6) EM78P813 8-bit OTP Micro-controller PAGE1 LCD Data buffer 7 6 LCDD7 LCDD6 Bit 0 ~ Example. MOV A,@0 MOV R9_PAGE1,A MOV RA_PAGE1,A MOV A,@0XAA MOV RB_PAGE1,A MOV A,RB_PAGE1 : 5 LCDD5 4 LCDD4 3 LCDD3 2 LCDD2 1 LCDD1 0 LCDD0 Bit 7 (LCDD0 ~ LCDD7) : LCD data buffer for LCD RAM reading or writing ;ADDRESS ;WRITE DATA 0XAA TO LCD RAM ;READ DATA FROM LCD RAM PAGE2 KEY Strobe Control Register 7 6 5 4 STRB7 STRB6 STRB5 STRB4 3 STRB3 2 STRB2 1 STRB1 0 STRB0 Bit 0 ~ Bit 7 (STRB0 ~ STRB7) : Key strobe control bits These key strobe control registers correspond to SEGMENT50 ~ SEGMENT57 or Port80 ~ Port87 (decided by CHIPSEL pin). Please refer KEYSTOBE explanation (RE page3). PAGE3 Tone 2 Control Register 7 6 5 T27 T26 T25 4 T24 3 T23 2 T22 1 T21 0 T20 Bit 0~Bit 7(T20~T27) : Tone generator1`s frequency divider and power control. Please refer to RA Page3 Tone1 control register for detail. RC Port C I/O Data , Data RAM data buffer , Tone 2 generator PAGE0 Port C I/O Data 7 6 5 4 3 2 PC7 PC6 PC5 PC4 PC3 PC2 Bit 0 ~ Bit 7 (PC0 ~ PC7) : 8-bit PORTC ( 0~7 ) I/O data register User can use IOC register to define input or output each bit. 1 PC1 0 PC0 PAGE1 Data RAM data buffer1 7 6 5 4 3 2 1 0 RAM1D7 RAM1D6 RAM1D5 RAM1D4 RAM1D3 RAM1D2 RAM1D1 RAM1D0 Bit 0 ~ Bit 7 (RAM1D0 ~ RAM1D7) : Data RAM data buffer1 for RAM reading or writing. Example. MOV A,@1 MOV RD_PAGE1,A MOV A,@0 MOV RE_PAGE1,A MOV A,@0x55 MOV RC_PAGE1,A MOV A,RC_PAGE1 : ;write data 0x55 to DATA RAM which address is "0001". ;read data __________________________________________________________________________________________________________________________________________________________________ * This specification is subject to change without notice. 32 2004/8/19 (V1.6) EM78P813 8-bit OTP Micro-controller PAGE2 KEY Strobe Control Register 7 6 5 4 3 2 STRB15 STRB14 STRB13 STRB12 STRB11 STRB10 1 STRB9 0 STRB8 Bit 0 ~ Bit 7 (STRB8 ~ STRB15) : Key strobe control bits These key strobe control registers correspond to SEGMENT58 ~ SEGMEN65 or Port90 ~ Port97 (decided by CHIPSEL pin). Please refer KEYSTOBE explanation (RE page3). PAGE3 Undefined Register 7 6 0 0 5 0 4 X 3 0 2 0 1 0 0 0 Bit 0~3, 5~7: Undefined register. These bits must keep to 0. RD PORT D I/O Data , Data RAM address , LCD control PAGE0 PORT D I/O Data , Data RAM address 7 6 5 4 3 PD7 PD6 PD5 PD4 PD3 Bit 0 ~ Bit 7 (PD0 ~ PD7) : 7-bit PORTD ( 0~6 ) I/O data register User can use IOC register to define input or output each bit. 2 PD2 1 PD1 0 PD0 PAGE1 Data RAM Address1(Low 8 bits) 7 6 5 4 3 2 1 0 RAM1A7 RAM1A6 RAM1A5 RAM1A4 RAM1A3 RAM1A2 RAM1A1 RAM1A0 Bit 0~Bit 7 (RAM1A0 ~ RAM1A7) : Data RAM address1 (address0 to address7) for RAM reading or writing PAGE2 LCD Control Register 7 6 5 IRS1 IRS0 4 Bias4 3 Bias3 2 Bias2 1 Bias1 0 Bias0 Bit 0 ~ Bit 4 (Bias0 ~ Bias4) : LCD operation voltage selection About the relation with VDD and V1 , please refer Fig.20 and 21. (Bias4 to Bias0) 00000 00001 00010 00011 00100 : 11101 11110 11111 VEV voltage Vref * (1-2/100) Vref * (1-3/100) Vref * (1-4/100) Vref * (1-5/100) Vref * (1-6/100) : Vref * (1-31/100) Vref * (1-32/100) Vref * (1-33/100) V1(1+Rb/Ra ratio = 2) 5.29V 5.24V 5.18V 5.13V 5.08V : 3.73V 3.67V 3.62V __________________________________________________________________________________________________________________________________________________________________ * This specification is subject to change without notice. 33 2004/8/19 (V1.6) EM78P813 8-bit OTP Micro-controller Bit 5~ Bit 6 (IRS0~IRS1) : Internal regulator resister ratio modulate . LCD driver bias voltage V1 = 2.7V x (1-Bias/100) x IRS rate ; If V1 larger than 5.4V,V1 will limit to 5.4V. IRS1 0 0 1 1 IRS0 0 1 0 1 (1+Rb/Ra) ratio 1.5 1.75 2.0 2.25 Charge pump Circuit ( Vref x 2 ) Vout = 5.4V Vsat = 5.3V VDD Regulator Circuit BIAS Circuit VEV = 1.805V ~ 2.65V + - Vref = 2.7V V1 = VEV*(1+Rb/Ra) Ra Bias4 ~ Bias 0 Rb Fig.23 The relation between VDD and V1 COMs VC1 ~ VC5 Bias generator LCD driver for COM and SEG V1 SEGs VC1 ~ VC5 Fig.24 The relation between BIAS and VC1 ~ VC5 __________________________________________________________________________________________________________________________________________________________________ * This specification is subject to change without notice. 34 2004/8/19 (V1.6) EM78P813 8-bit OTP Micro-controller SEG 0 SEG 1 : : frame VC1 VC2 VC3 VC4 COM 0 COM 1 COM 2 : : COM 0 VC5 Gnd VC1 VC2 VC3 VC4 VC5 Gnd VC1 VC2 COM 1 COM 2 VC3 VC4 VC5 Gnd VC1 VC2 SEG 0 VC3 VC4 VC5 Gnd VC1 VC2 SEG 1 VC3 VC4 VC5 Gnd VC1 SEG 1 - COM 2 VSS -VC1 Fig.25 1/5,1/6,1/7 bias LCD COMMON and SEGMENT waveform Bit 7 : Unused __________________________________________________________________________________________________________________________________________________________________ * This specification is subject to change without notice. 35 2004/8/19 (V1.6) EM78P813 8-bit OTP Micro-controller PAGE3 Undefined register This register is not allowed to used. RE Interrupt flag1 , Data RAM address1(H) CAS , LCD Control , Key Scan , PAGE0 Interrupt flag1 7 6 5 4 3 2 1 INT7 INT6 INT5 INT4 INT3 INT2 INT1 Bit 0 (INT0) : External INT0 pin interrupt flag If PORT70 has a falling edge trigger signal. CPU will set this bit. Bit 1 (INT1) : External INT1 pin interrupt flag If PORT71 has a falling edge trigger signal. CPU will set this bit. Bit 2 (INT2) : External INT2 pin interrupt flag If PORT72 has a falling edge trigger signal. CPU will set this bit. Bit 3 (INT3) : External INT3 pin interrupt flag If PORT73 has a falling edge trigger signal. CPU will set this bit. Bit 4 (INT4) : External INT4 pin interrupt flag If PORT74 has a falling edge trigger signal. CPU will set this bit. Bit 5 (INT5) : External INT5 pin interrupt flag If PORT75 has a falling edge trigger signal. CPU will set this bit. Bit 6 (INT6) : External INT6 pin interrupt flag If PORT76 has a falling edge trigger signal. CPU will set this bit. Bit 7 (INT7) : External INT7 pin interrupt flag If PORT77 has a falling (or rising and falling) edge trigger signal. CPU will set this bit. Signal INT0 : INT6 INT7 Trigger Falling edge Falling/Falling & rising edge Controlled by CONT register 0 INT0 PAGE1 Data RAM Address1(H) 7 6 5 4 3 2 1 0 RAM1A13 RAM1A12 RAM1A11 RAM1A10 RAM1A9 RAM1A8 Bit 0~Bit 5(RAM1A8 ~ RAM1A13) : Data RAM address (address8 to address13) for RAM reading. Bit 6~Bit 7 : Unused PAGE2 CAS , LCD Control , Key Scan 7 6 5 4 3 CAS KEYSTROB KEYSCAN LCD1 2 LCD0 1 0 LCDM1 LCDM0 Bit 0~Bit 1(LCDM0~LCDM1) : LCD common mode, bias select and COM/SEG switch control bits LCDM1 LCDM0 COM output mode LCD bias COM/SEG switch 0 0 32 common 1/7 COM 16 ~ COM 31 select 0 1 24 common 1/6 COM 16 ~ COM 23 , SEG98 ~ SEG 105 select 1 X 16 common 1/5 SEG 98 ~ SEG 111 select __________________________________________________________________________________________________________________________________________________________________ * This specification is subject to change without notice. 36 2004/8/19 (V1.6) EM78P813 8-bit OTP Micro-controller Bias 1/5 1/6 1/7 VC1 V1 V1 V1 VC2 4/5*V1 5/6*V1 6/7*V1 VC3 3/5*V1 4/6*V1 5/7*V1 VC4 2/5*V1 2/6*V1 2/7*V1 VC5 1/5*V1 1/6*V1 1/7*V1 Bit 2~Bit 3(LCD0~LCD1) : LCD operation function definition. LCD1 LCD0 LCD operation 0 0 Disable 0 1 Blanking 1 0 Reserved 1 1 LCD enable __________________________________________________________________________________________________________________________________________________________________ * This specification is subject to change without notice. 37 2004/8/19 (V1.6) EM78P813 8-bit OTP Micro-controller COM2 V1 V2 V4 V5 GND SEG V1 V2 V4 V5 GND V1 V2 V4 V5 30us GND Fig.26 key scan waveform for 1/16 duty Bit 5 (KEYSTRB) : Key strobe enable control bit 0/1 disable/enable key strobe signal , if you set this bit , segment will switch to strobe signal temporally and output zero signal ( one instruction long ) one by one from segment 50 to segment 65. During one segment strobe time, CPU will check port7(0:3) equal to "1111" or not. If not, CPU will latch a zero at RB PAGE1 and RC PAGE1 one by one depends on which segment strobe. After strobe, this bit will be cleared . Fig.27 is key strobe signal. One instruction REGISTER RB(0) RB(1) RB(2) RB(3) RB(4) RB(5) RB(6) RB(7) RC(0) RC(1) RC(2) RC(3) RC(4) RC(5) RC(6) RC(7) STROBE SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 SEG65 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 Fig.27 key strobe signal __________________________________________________________________________________________________________________________________________________________________ * This specification is subject to change without notice. 38 2004/8/19 (V1.6) EM78P813 8-bit OTP Micro-controller Fig.28 show the relationship between KEYSCAN, KEYSTROBE and segments. Fig.29 is key scan flow by interrupt trigger. RELATION BETW EEN SEGM ENT , KEYSCAN, KEY STROBE KEY SCAN PULSE KEY SCAN CONTROL SEG50~SEG65 KEY STROBE SIGNAL 0 M UX 1 KEYSTROBE Fig.28 KEYSCAN, KEYSTROBE Set port7(3:0) input port7 pull high enable key scan signal Set INT0~INT3 interrupt ENI N Interrupt occur? Y Enable main clock (Normal mode) program delay Analysis external interrupt ( column key ) set strobe function enable keystrobe program delay read strobe data (row key) Execution key function Get the key location Fig.29 key scan flow by interrupt trigger Bit 6 : Unused Bit 7 (CAS) : CALL WAITING decoding output 0/1 CW data valid / No data __________________________________________________________________________________________________________________________________________________________________ * This specification is subject to change without notice. 39 2004/8/19 (V1.6) EM78P813 8-bit OTP Micro-controller PAGE3 UART transmitter data buffer 7 6 5 4 URT7 URT6 URT5 URT4 RF Interrupt flag 7 6 RBF/SDT FSK/CW 3 URT3 2 URT2 1 URT1 0 URT0 Bit 0~Bit 7(URT0~URT7) : Low 8 bit UART transmitter data buffer 5 - 4 UART 3 DED 2 CNT2 1 CNT1 0 TCC "1" means interrupt request, "0" means non-interrupt Bit 0 (TCC) : TCC timer overflow interrupt flag Set when TCC timer overflows . Bit 1 (CNT1) : Counter1 timer overflow interrupt flag Set when counter1 timer overflows. Bit 2 (CNT2) : Counter2 timer overflow interrupt flag Set when counter2 timer overflows . Bit 3 (DED) : Interrupt flag of Differential Energy Detector (DED) output data. If DEDD(RE page2 bit7) has a falling edge signal (or falling & rising edge signal , switch by IOCE page1 bit5), CPU will set this bit. Bit 4 (UART) : Universal Asynchronous Receiver Transmitter interrupt flag. When transmitter buffer empty , receiver buffer full or receiver data error, this bit will be set. Bit 5Undefined register. Note that this bit is not ensured to be a fix value. Bit 6 (FSK/CW) : FSK data or Call waiting data interrupt flag. If FSKDATA or CAS has a falling edge trigger signal, CPU will set this bit. Bit 7 ( RBF/STD) : SPI data transfer complete or DTMF receiver signal valid interrupt If serial IO 's RBF signal has a rising edge signal (RBF set to "1" when transfer data completely), CPU will set this bit. Or DTMF receiver's STD signal has a rising edge signal (DTMF decode a DTMF signal). IOCF is the interrupt mask register. User can read and clear. Trigger edge as the table Signal Trigger PAGE2 External Data ROM 7 6 5 EXA8 EXA7 EXA6 PAGE2 External Data ROM 7 6 5 EXA16 EXA15 EXA14 4 EXA5 3 EXA4 2 EXA3 1 EXA2 0 EXA1 Bit 0~Bit 7(EXA1~EXA8) : Expanding Data ROM start address A1~A8 4 EXA13 3 EXA12 2 EXA11 1 EXA10 0 EXA9 Bit 0~Bit 7(EXA9~EXA16) : Expanding Data ROM start address A9~A16 __________________________________________________________________________________________________________________________________________________________________ * This specification is subject to change without notice. 40 2004/8/19 (V1.6) EM78P813 8-bit OTP Micro-controller PAGE3 Undefined register This register is not allowed to used. R10~R3F (General Purpose Register) R10~R3F (Banks 0 ~ 3) : All of them are general purpose registers VII.3 Special Purpose Registers A (Accumulator) Internal data transfer, or instruction operand holding It's not an addressable register. CONT ( Control Register ) 7 6 INT/EDGE INT 5 TS 4 DAEN 3 PAB 2 RSR2 1 RSR1 0 RSR0 Bit 0 ~ Bit 2 (PSR0 ~ PSR2) : TCC/WDT prescaler bits PSR2 0 0 0 0 1 1 1 1 PSR1 0 0 1 1 0 0 1 1 PSR0 0 1 0 1 0 1 0 1 TCC rate 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256 WDT rate 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128 Bit 3(PAB) : Prescaler assignment bit 0/1 TCC/WDT Bit 4 (DAEN) : Current DA enable control 0/1 disable/enable Bit 5 (TS) : TCC signal source 0/1 Instruction clock / 16.384K Hz Instruction clock = MCU clock/2, Refer to RA Bit 4 ~ Bit 6 for PLL and Main clock selection. See Fig.15. Bit 6 (INT) : INT enable flag 0 interrupt masked by DISI or hardware interrupt 1 interrupt enabled by ENI/RETI instructions Bit 7(INT_EDGE) : interrupt edge type of P77 0 P77 's interruption source is a rising edge signal and falling edge signal. 1 P77 's interruption source is a falling edge signal. CONT register is readable (CONTR) and writable (CONTW).There is an 8-bit counter available as prescaler for the TCC or WDT. The prescaler is available for the TCC only or WDT only at the same time. An 8 bit counter is available for TCC or WDT determined by the status of the bit 3 (PAB) of the CONT register. See the prescaler ratio in CONT register.Fig.25 depicts the circuit diagram of TCC/WDT. Both TCC and prescaler will be cleared by instructions which write to TCC each time. The prescaler will be cleared by the WDTC and SLEP instructions, when assigned to WDT mode. The prescaler will not be cleared by SLEP instructions, when assigned to TCC mode. __________________________________________________________________________________________________________________________________________________________________ * This specification is subject to change without notice. 41 2004/8/19 (V1.6) EM78P813 8-bit OTP Micro-controller Data Bus Instruction clock 16.384kHz M U X M U X PAB SYNC 2 cycles TCC(R1) TS TCC overflow interrupt W DT WDTE M U X PAB 8-bit Counter PSR0 ~ PSR2 8-to-1 MUX MUX PAB WDT timeout Fig.30 Block diagram of TCC and WDT IOC5 Address Automatic Increase/Decrease control , Data RAM data buffer2 PAGE0 Address Automatic Increase/Decrease control register 7 6 5 4 3 2 1 0 DA2_ID DA1_ID DO_ID LCD_ID DA2_IDEN DA1_IDEN DO_IDEN LCD_IDEN Bit 0 (LCD_IDEN) : Enable on_chip LCD RAM address Increase/Decrease Enable Function. If set this bit, LCD address flag will increase or decrease after access ( read or write ) LCD data. 1/0 Enable / Disable **EM78813 provided 32x98 dot LCD driver and it's SEGMENT address(COM0~COM7) is 0x00~0x7F(RA PAGE1). When using 32 x 98 LCD driving mode, LCD RAM will mapping to 0x000~0x061,0x080~0x0E1,0x100~0x161 and 0x181~0x1E1. If enable on_chip LCD RAM address auto_increase function , After access data from LCD driver in address 0x061, LCD RAM address will auto_increase to 0x062 and it will over LCD range. User must assign address to 0x080 when LCD RAM address point to 0x061. Bit 2 (DO_IDEN) : Enable DATA ROM address flag Increase/Decrease Enable Function. If set this bit, DATA ROM address will increase or decrease after access ( read or write ) DATA ROM data. 1/0 Enable / Disable Bit 3(DA1_IDEN) : Enable DATA RAM address flag1(RD and RE register) Increase/Decrease Enable Function. If set this bit, DATA RAM address will increase or decrease after access ( read or write ) DATA RAM data (RC register). 1/0 Enable / Disable Bit 4 (DA2_IDEN) : Enable DATA RAM address flag2(IOC6 and IOC7) Increase/Decrease Enable Function. If set this bit, DATA RAM address will increase or decrease after access ( read or write ) DATA RAM data (IOC5 register). 1/0 Enable / Disable Bit 5 (LCD_ID) : on_chip LCD RAM address automatic increase/decrease switch. Set to 1 means auto_increase, clear to 0 means auto_decrease. 1/0 auto increase / auto decrease Bit 6 (DO_ID) : DATA ROM address automatic increase/decrease switch. Set to 1 means auto_increase, clear to 0 means auto_decrease. 1/0 auto increase / auto decrease Bit 7 (DA1_ID) : DATA RAM address(RD and RE register) automatic increase/decrease switch. Set to 1 means auto_increase, clear to 0 means auto_decrease. __________________________________________________________________________________________________________________________________________________________________ * This specification is subject to change without notice. 42 2004/8/19 (V1.6) EM78P813 8-bit OTP Micro-controller 1/0 auto increase / auto decrease Bit 7 (DA2_ID) : DATA RAM address(IOC6 and IOC7 register) automatic increase/decrease switch. Set to 1 means auto_increase, clear to 0 means auto_decrease. 1/0 auto increase / auto decrease PAGE1 Data RAM data buffer2 7 6 5 4 3 2 1 0 RAM2D7 RAM2D6 RAM2D5 RAM2D4 RAM2D3 RAM2D2 RAM2D1 RAM2D0 Bit 0 ~ Bit 7 (RAM1D0 ~ RAM1D7) : Data RAM data buffer for RAM reading or writing. Collocation RC~RE PAGE2 , user can move a large number continue data from an address to another in data RAM. Example(move data from 0x0000 to 0x1000): BC MOV IOW BS BS BC MOV MOV MOV IOW MOV IOW MOV IOW MOV IOW : : R3,@5 A , @0xF0 0x05 R3 , @5 R3 , @6 R3 , @7 A , @0x00 0x0D , A 0x0E , A 0x06 A , @0x10 0x07 A , 0x0C 0x05 A , 0x0C 0x05 ;Enable Rata RAM flag1 and flag2 auto_increase function :Set correspond PAGE ;Assign DATA RAM index1 start address"0x0000" ; Assign DATA RAM index2 start address"0x1000" ;Read data from index1(address:0x0000) ;Write data to index2(address:0x1000) ;Read data from index1(address:0x0001) ;Write data to index2(address:0x1001) IOC6 PORT 6 I/O Control , Data RAM address(L) PAGE0 PORT 6 I/O Control 7 6 5 4 3 IOC67 IOC66 IOC65 IOC64 IOC63 Bit 0~Bit 7 (IOC60 ~ IOC67) : PORT6(0~7) I/O direction control register 0 put the relative I/O pin as output 2 IOC62 1 IOC61 0 IOC60 1 put the relative I/O pin into high impedance PAGE1 Data RAM Address2(L) 7 6 5 4 3 2 1 0 RAM2A7 RAM2A6 RAM2A5 RAM2A4 RAM2A3 RAM2A2 RAM2A1 RAM2A0 Bit 0~Bit 7 (RAM2A0 ~ RAM2A7) : Data RAM address (address0 to address7) for RAM reading or writing IOC7 PORT 7 I/O Control , Data RAM Address2(H) PAGE0 PORT 7 I/O Control 7 6 5 4 3 IOC77 IOC76 IOC75 IOC74 IOC73 Bit 0~Bit 7 (IOC70 ~ IOC77) : PORT7(0~7) I/O direction control register 0 put the relative I/O pin as output 1 put the relative I/O pin into high impedance 2 IOC72 1 IOC71 0 IOC70 __________________________________________________________________________________________________________________________________________________________________ * This specification is subject to change without notice. 43 2004/8/19 (V1.6) EM78P813 8-bit OTP Micro-controller PAGE1 Data RAM address2(H) 7 6 5 4 3 2 1 0 RAM2A13 RAM2A12 RAM2A11 RAM2A10 RAM2A9 RAM2A8 Bit 0~Bit 5 (RAM2A8 ~ RAM2A13) : Data RAM address (address8 to address13) for RAM reading or writing Bit 6~Bit 7 : Unused IOC8 PORT 8 I/O Control ,Port8 and Port9 IO/SEG&COM Control PAGE0 PORT 8 I/O Control 7 6 5 4 3 2 IOC87 IOC86 IOC85 IOC84 IOC83 IOC82 Bit 0 ~ Bit 7 (IOC80 ~ IOC87) : PORT8(0~7) I/O direction control register 0 put the relative I/O pin as output 1 IOC81 0 IOC80 1 put the relative I/O pin into high impedance PAGE1 IO/SEG&COM Control Register 7 6 5 4 LCDDV1 LCDDV0 - 3 P9SH 2 P9SL 1 P8SH 0 P8SL Bit 0 (P8SL) : Switch low nibble I/O Port8 or LCD segment output for share pins SEGxx/P8x pins 0 select normal P80 ~ P83 for low nibble PORT8 1 select SEG66~SEG69 output for LCD SEGMENT output. Bit 1 (P8SH) : Switch high nibble I/O Port8 or LCD segment output for share pins SEGxx/P8x pins 0 select normal P84 ~ P87 for high nibble PORT8 1 select SEG70 ~ SEG73 output for LCD SEGMENT output. Bit 2 (P9SL) : Switch low nibble I/O Port9 or LCD segment output for share pins 0 select normal P90 ~ P93 for low nibble PORT9 1 select SEG74~SEG77 output for LCD SEGMENT output. Bit 3 (P9SH) : Switch low nibble I/O Port9 or LCD segment output for share pins 0 select normal P94 ~ P97 for high nibble PORT9 1 select SEG78~SEG81 output for LCD SEGMENT output. Bit 4~Bit 5(LCDDV0~LCDDV1) : LCD driver's driving ability control LCDDV1 0 0 1 1 LCDDV0 0 1 0 1 Driving mode Normal mode (ratio = 1) Weak mode (ratio = 1/2) Strong mode (ratio = 2) Maximum mode (ratio = 4) LCDDV0 ~ LCDDV1 are used to select the driving ability of LCD driver. The driving ability is Maximum mode > Strong mode > Normal mode > Weak mode by 1/2 ratio individually. The larger driving ability it is selected, the larger output loading of LCD driver output can be afforded and the more current consumption is occurred. It depends on user's application. Bit 6~ Bit7: Undefined register. These two bits are not allowed to use. IOC9 PORT9 I/O Control , Port B IO/SEG Control PAGE0 PORT 9 I/O Control 7 6 5 4 3 IOC97 IOC96 IOC95 IOC94 IOC93 Bit 0 ~ Bit 7 (IOC90 ~ IOC97) : PORT9(0~7) I/O direction control register 0 put the relative I/O pin as output 1 put the relative I/O pin into high impedance 2 IOC92 1 IOC91 0 IOC90 __________________________________________________________________________________________________________________________________________________________________ * This specification is subject to change without notice. 44 2004/8/19 (V1.6) EM78P813 8-bit OTP Micro-controller PAGE1 Port B IO/SEG Control Register 7 6 5 4 PBS7 PBS6 PBS5 PBS4 3 PBS3 2 PBS2 1 PBS1 0 PBS0 Bit 0~Bit 7 (PBS0~PBS7) : Switch I/O PORTB or LCD segment(com) output for share pins COMxx/SEGxx/PORTB pins 0 select normal PORTB I/O 1 select output for LCD COM/SEGMENT output. IOCA Stack point , Port C IO/SEG Control PAGE0 STACK Point 7 6 5 4 STKP4 3 STKP3 2 STKP2 1 STKP1 0 STKP0 Bit 0 ~ Bit 5 (STKP0 ~ STKP4) : Stack Point selection bits Stack4 STKP3 STKP2 STKP1 STKP0 Stack Point 0 0 0 0 0 Stack 1 0 0 0 0 1 Stack 2 0 0 0 1 0 Stack 3 0 0 0 1 1 Stack 4 : : : : : : : : : : : : 1 0 1 1 0 Stack 22 1 0 1 1 1 Stack 23 1 1 0 0 0 Stack 24 User can read bit 5 .. bit 0 to understand how many stack layer that program used . Bit 4 .. bit 0 is a six bit counter. The counter will incrementally after user use internal , external interrupt or "CALL" instruction and it will decrement when user use "RET" or "RETI" instruction. These five bits are read only bits. Bit 5~Bit 7 : Unused PAGE1 Port C IO/SEG Control Register 7 6 5 4 PCS7 PCS6 PCS5 PCS4 3 PCS3 2 PCS2 1 PCS1 0 PCS0 Bit 0~Bit 7 (PCS0~PCS7) : Switch I/O PORTC or LCD segment(com) output for share pins COMxx/SEGxx/PORTC pins 0 select normal PORTC I/O 1 select output for LCD COM/SEGMENT output. IOCB PORT B I/O Control ,External LCD driver interface (for EMC 65x132) PAGE0 PORT B I/O Control 7 6 5 4 3 2 1 IOCB7 IOCB6 IOCB5 IOCB4 IOCB3 IOCB2 IOCB1 Bit 0~Bit 7 (IOCB0~IOCB7) : PORTB(0~7) I/O direction control register 0 put the relative I/O pin as output 1 put the relative I/O pin into high impedance 0 IOCB0 PAGE1 External LCD Driver controller 7 6 5 4 EXA17 CWPWR RES1 RSE0 3 CSS 2 CSSON 1 DIS 0 EXLCD Bit 0(EXLCD) : Internal/External LCD driver switch. 0/1 Internal only/Internal and External LCD driver control __________________________________________________________________________________________________________________________________________________________________ * This specification is subject to change without notice. 45 2004/8/19 (V1.6) EM78P813 8-bit OTP Micro-controller If EXLCD equal to 0, internal LCD driver selected . PortB and PortC output are decided on IOC9 and IOCA Page1. When EXLCD equal to 1, PortB and PortC are switch to external LCD driver control pin. At this time, when user execute read or write PORTB instruction, PORTC timing characteristic plot is follow below. Tah A0(PC4) CS(PC0/PC1) Taw Tcyc Tcc Tdh Tds WR(PC2)/ RD(PC3) PORTB PORTB Tacc DATA Toh DATA Fig.31 timing characteristic of external LCD driver data read/write Symbol Tah Taw Tcyc Tcc Tds Tdh Tacc Toh Tah : Address hold time Taw : Address setup time Tcyc : System cycle time Tcc : Pulse width Tds : Data setup time Tdh : Data hold time Tacc : Read access time Toh : Output disable time User can operate in coordination on chip Data ROM address automatic increase function to write a large number of data from internal Data ROM to external LCD RAM. Example( To collocate EM9L8580 LCD driver ): START: MOV A , @0x0C; IOW IOC5_PAGE0 ;Set Data ROM address automatic increase after read/write data MOV A , @0x09 IOW IOCB_PAGE1 ;External LCD driver chip 1 INSTRUCTION mode select . MOV A , @0xB0; MOV RB_PAGE0 , A ;Set external LCD driver start address PAGE 0 MOV A , @0x10 MOV RB_PAGE0 , A MOV A , @0x00 __________________________________________________________________________________________________________________________________________________________________ Applicable pins A0 A0 A0 WR/RD D0 ~D7 D0 ~D7 D0 ~D7 D0 ~D7 Rated value Min Max 0 0 150 60 20 10 60 10 40 Unit ns * This specification is subject to change without notice. 46 2004/8/19 (V1.6) EM78P813 8-bit OTP Micro-controller MOV MOV MOV MOV MOV MOV IOW CN1: MOV A , R6_PAGE1 ;read data from Data ROM and address flag increase MOV RB_RAGE0 , A ;write data to external LCD driver. JMP LOOP Bit 1(DIS) : External LCD driver DATA/INSTRUCTION switch. 0/1 INSTRACTION/DATA When EXLCD equal to 1 and DIS bit equal to 0 , MUC will transmit/receive INSTRUCTION. A0(PortC7) will output 0. If DIS bit set to 1, MUC will transmit/receive DATA. A0(PortC4) will output 1 Bit 2(CSSON) : External LCD driver select enable CSSON 0 1 1 CSS0 X 0 1 LOW CS1 CS2 CS1..CS2 HIGH CS1,CS2 CS2 CS1 RB_PAGE0 , A ; Set external LCD driver start address Column 0 A , @0x00; R7_PAGE1 , A; R8_PAGE1 , A; R9_PAGE1 , A ;Start address : 0x00000 A , @0x0B IOCB_PAGE1 ;select data mode Example( for EMC 65x132 LCD driver ): MOV A, @0x01 IOW IOCB_PAGE1 ;Select external LCD driver & INSTRUCTURE mode MOV A,@0xB0 MOV RB,A ;Select external LCD driver COM0 MOV A,@0x10 MOV RB,A ;Select external LCD driver SEG Upper 4-bit = 0 MOV A,@0x00 MOV RB,A ;Select external LCD driver SEG Lower 4-bit = 0 MOV A,@0x03 IOW IOCB_PAGE1 ;switch to DATA mode MOV A,@0xFF MOV RB,A ;write 0xFF to COM0 &SEG0 : User must assign external LCD address at first time. After writing or reading the display data, The SEGMENT address is automatically incremented. So that the MUC can continuously write or read data to the address. Bit 3(CSS) : External LCD driver chip select bit. 0/1 chip1 / chip2 Bit 4..Bit 5(RES0 ~ RES1) : Touch panel bias resister switch.. Bit 6(CWPWR) : CAS decoder power control. 0/1 Power off / Power on. Bit 7(EXA17) : Expand Data ROM start address MSB. This bit can not set unless CHIPSEL and EXSEL pin connect to VDD. __________________________________________________________________________________________________________________________________________________________________ * This specification is subject to change without notice. 47 2004/8/19 (V1.6) EM78P813 8-bit OTP Micro-controller IOCC PORT C I/O Control , Port 6 Pull high register PAGE0 PORT C I/O Control 7 6 5 4 3 IOCC7 IOCC6 IOCC5 IOCC4 IOCC3 Bit 0~Bit 7 (IOCC0~IOCC7) : PORTC(0~7) I/O direction control register 0 put the relative I/O pin as output 1 put the relative I/O pin into high impedance 2 IOCC2 1 IOCC1 0 IOCC0 PAGE1 Port 6 Pull High Register 7 6 5 PH67 PH66 PH65 4 PH64 3 PH63 2 PH62 1 PH61 0 PH60 Bit 0~Bit 7(PH60~PH67) : PORT6(0~7) pull high control register 0 disable pull high function. 1 enable pull high function IOCD PORT D I/O Control , Port 7 Pull high register PAGE0 PORT D I/O Control 7 6 5 4 3 IOCD7 IOCD6 IOCD5 IOCD4 IOCD3 Bit 0~Bit 6 (IOCD0~IOCD6) : PORTD(0~6) I/O direction control register 0 put the relative I/O pin as output 1 put the relative I/O pin into high impedance 2 IOCD2 1 IOCD1 0 IOCD0 PAGE1 Port 7 Pull High Register 7 6 5 PH77 PH76 PH75 4 PH74 3 PH73 2 PH72 1 PH71 0 PH70 Bit 0~Bit 7(PH70~PH77) : PORT7(0~7) pull high control register 0 disable pull high function. 1 enable pull high function IOCE Interrupt mask , Differential Energy Detect PAGE0 Interrupt Mask Register1 7 6 5 4 INT7 INT6 INT5 INT4 Bit 0~Bit 7 : Interrupt enable bits. 0/1 disable interrupt/enable interrupt 3 INT3 2 INT2 1 INT1 0 INT0 PAGE1 Differential Energy Detect 7 6 5 VRSEL DEDD EDGE 4 3 2 1 0 WUEDD CW_SMB DEDCLK DEDPWR DEDTHD Bit 0(DEDTHD) : The minimum detection threshold of Differential Energy Detector (DED) 0/1 -45dBm/-30dBm Bit 1 (DEDPWR) : Power control of Differential Energy Detector (DED) 0/1 Power off / Power on Bit 2 (DEDCLK) : Operating clock for Differential Energy Detector (DED) 0/1 32.768kHz/3.5826MHz This bit is used to select operating clock for Differential Energy Detector (DED). When this bit is set to "1", the PLL is also enabled regardless of RA bit 6 (ENPLL) . At this time, the Energy detector works at high frequency __________________________________________________________________________________________________________________________________________________________________ * This specification is subject to change without notice. 48 2004/8/19 (V1.6) EM78P813 8-bit OTP Micro-controller mode. When this bit is set to "0", the Energy Detector works at low frequency mode. The difference between high frequency and low frequency is as follows. DEDPWR DEDCLK ENPLL Energy detector clock Main CLK 0 X X X Decision by ENPLL 1 0 0 32.768 KHz Disable 1 0 1 32.768 KHz Enable 1 1 0 3.5826 MHz Enable 1 1 1 3.5826 MHz Enable PS. "X" means don't care Bit 3(CW_SMB) : Call Waiting / short message receiver switch 0 Short message mode select. 5.5% CAS tone accepted frequency range deviation.(Protocol : 5%) 1 Call Waiting mode select. CAS tone accepted frequency range deviation is decided on CODE Option Register bit 5 ( 1:for Europe and USA / 0:for China ) Bit 4 (WUEDD) : Wake-up control of Energy Detector (DED) output data 1/0 enable/disable Bit 5 (EDGE) : Wake-up and interrupt trigging edge control of Energy Detector (DED) output 1/0 Falling edge trig. / Rising edge and Falling edge trig. Bit 6(DEDD) : Output data of Differential Energy Detector (DED) If input signal from TIP/EGIN1 and RING/EGIN2 pin to Differential Energy Detector is over the threshold level setting at IOCE PAGE 2 bit 0 (DEDTHD), the DED will extract the zero-crossing pulse waveform corresponding to input signal. Bit 7 (VRSEL) : Reference voltage VR selection bit for Comparator 0 VR = VDD 1 VR = 2.0V When this bit is set to "0", V2_0 ref. circuit will be powered off. 2.0V ref. circuit is only powered on when this bit and RA page2 bit 7(CMPEN) are all set to "1". IOCF Interrupt Mask Register2 7 6 5 RBF/STD FSK/CW 0 Bit 0~Bit 4, Bit6~Bit7 : Interrupt enable bits. 4 UART 3 DED 2 CNT2 1 CNT1 0 TCC 0/1 disable interrupt/enable interrupt Bit4: Undefined register. This bit must keep to 0. __________________________________________________________________________________________________________________________________________________________________ * This specification is subject to change without notice. 49 2004/8/19 (V1.6) EM78P813 8-bit OTP Micro-controller VII.4 I/O PORT PCRD Q P R C L D CLK PCWR Q PORT Q P R C L D CLK PDWR IOD Q PDRD 0 1 M U X Fig.32 The circuit of I/O port and I/O control register The I/O registers are bi-directional tri-state I/O ports. The I/O ports can be defined as "input" or "output" pins by the I/O control registers under program control. The I/O registers and I/O control registers are both readable and writable. The I/O interface circuit is shown in Fig.27 VII.5 RESET The RESET can be caused by (1) Power on voltage detector reset (POVD) and power on reset (2) WDT timeout. (if enabled and in GREEN or NORMAL mode) (3) /RESET pin pull low __________________________________________________________________________________________________________________________________________________________________ * This specification is subject to change without notice. 50 2004/8/19 (V1.6) EM78P813 8-bit OTP Micro-controller address R register page0 1 2 3 4 5 6 7 8 9 A B C D E F ---00xxxxxx x0000000 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00000xx0 xxxxxxxx xxxxxxxx xxxxxxxx 00000000 00000000 R register page1 00000000 --xxxxxxxx 00000000 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx R register page2 00000000 --10001000 00000000 00000000 00000000 x0000000 00000xxx 00000000 11111111 11111111 x0011111 10000000 xxxxxxxx R register page3 xxxxxxxx --xxx00000 xxxx0000 00000000 00000000 xxxxxxxx xxxx0000 00000000 00000000 00000000 xxxxxxxx xxxxxxxx xxxxxxxx IOC register page0 IOC register page1 11110000 11111111 11111111 11111111 11111111 00000000 11111111 11111111 11111111 00000000 00000000 xxxxxxxx xxxxxxxx xxxxxxxx 00000000 00000000 00000000 00xx0000 00000000 00000000 0x000000 -- VII.6 wake-up The controller provided sleep mode for power saving. SLEEP mode , RA(7)=0 + "SLEP" instruction . The controller will turn off all the CPU and crystal. Other circuit with power control like key tone control or PLL control (which has enable register), user has to turn it off by software. Wake-up from SLEEP mode : (1) WDT time out (2) external interrupt (3) /RESET pull low All these cases will reset controller , and run the program at address zero. The status just like the power on reset. Be sure to enable circuit at case (1) or (2). VII.7 Interrupt RE and RF is the interrupt status register which records the interrupt request in flag bits. IOCE and IOCF is the interrupt mask register. TCC timer, Counter1 and Counter2 are internal interrupt source. P70 ~ P77(INT0 ~ INT7) are external interrupt input which interrupt sources are come from the external. If the interrupts are happened by these interrupt sources, then RE or RF register will generate '1' flag to corresponding register if you enable IOCE or IOCF register. Global interrupt is enabled by ENI instruction and is disabled by DISI instruction. When one of the interrupts (when enabled) generated, will cause the next instruction to be fetched from address 008H. Once in the interrupt service routine the source of the interrupt can be determined by polling the flag bits in the RE and RF register. The interrupt flag bit must be cleared in software before leaving the interrupt service routine and enabling interrupts to avoid recursive interrupts. __________________________________________________________________________________________________________________________________________________________________ * This specification is subject to change without notice. 51 2004/8/19 (V1.6) EM78P813 8-bit OTP Micro-controller VII.8 Instruction Set Instruction set has the following features: (1) Every bit of any register can be set, cleared, or tested directly. (2) The I/O register can be regarded as general register. That is, the same instruction can operates on I/O register. The symbol "R" represents a register designator which specifies which one of the 64 registers (including operational registers and general purpose registers) is to be utilized by the instruction. Bits 6 and 7 in R4 determine the selected register bank. "b'' represents a bit field designator which selects the number of the bit, located in the register "R'', affected by the operation. "k'' represents an 8 or 10-bit constant or literal value. INSTRUCTION HEX MNEMONIC OPERATION STATUS Instruction BINARY AFFECTED cycle 0 0000 0000 0000 0000 NOP No Operation None 1 0 0000 0000 0001 0001 DAA Decimal Adjust A C 1 0 0000 0000 0010 0002 CONTW None 1 A CONT 0 0000 0000 0011 0003 SLEP 1 0 WDT, Stop oscillator T,P 0 0000 0000 0100 0004 WDTC T,P 1 0 WDT 0 0000 0000 rrrr 000r IOW R None 1 A IOCR 0 0000 0001 0000 0010 ENI Enable Interrupt None 1 0 0000 0001 0001 0011 DISI Disable Interrupt None 1 0 0000 0001 0010 0012 RET None 2 [Top of Stack] PC None 2 0 0000 0001 0011 0013 RETI [Top of Stack] PC Enable Interrupt 0 0000 0001 0100 0014 CONTR None 1 CONT A 0 0000 0001 rrrr 001r IOR R None 1 IOCR A 0 0000 0010 0000 0020 TBL Z,C,DC 2 R2+A R2 bits 9,10 do not clear 0 0000 01rr rrrr 00rr MOV R,A None 1 A R 0 0000 1000 0000 0080 CLRA Z 1 0A 0 0000 11rr rrrr 00rr CLR R Z 1 0R 0 0001 00rr rrrr 01rr SUB A,R Z,C,DC 1 R-A A 0 0001 01rr rrrr 01rr SUB R,A Z,C,DC 1 R-A R 0 0001 10rr rrrr 01rr DECA R Z 1 R-1 A 0 0001 11rr rrrr 01rr DEC R Z 1 R-1 R 0 0010 00rr rrrr 02rr OR A,R Z 1 A RA 0 0010 01rr rrrr 02rr OR R,A Z 1 A R R 0 0010 10rr rrrr 02rr AND A,R Z 1 A& RA 0 0010 11rr rrrr 02rr AND R,A Z 1 A&R R 0 0011 00rr rrrr 03rr XOR A,R Z 1 ARA 0 0011 01rr rrrr 03rr XOR R,A Z 1 ARR 0 0011 10rr rrrr 03rr ADD A,R Z,C,DC 1 A+RA 0 0011 11rr rrrr 03rr ADD R,A Z,C,DC 1 A+RR 0 0100 00rr rrrr 04rr MOV A,R Z 1 RA 0 0100 01rr rrrr 04rr MOV R,R Z 1 RR 0 0100 10rr rrrr 04rr COMA R Z 1 /R A 0 0100 11rr rrrr 04rr COM R Z 1 /R R 0 0101 00rr rrrr 05rr INCA R Z 1 R+1 A 0 0101 01rr rrrr 05rr INC R Z 1 R+1 R 0 0101 10rr rrrr 05rr DJZA R None 2 if skip R-1 A, skip if zero 0 0101 11rr rrrr 05rr DJZ R None 2 if skip R-1 R, skip if zero __________________________________________________________________________________________________________________________________________________________________ * This specification is subject to change without notice. 52 2004/8/19 (V1.6) EM78P813 8-bit OTP Micro-controller 0 0110 00rr 0 0110 01rr 0 0110 10rr 0 0110 11rr 0 0111 00rr 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0111 0111 0111 100b 101b 110b 111b 00kk 01kk 1000 1001 1010 1011 1100 01rr 10rr 11rr bbrr bbrr bbrr bbrr kkkk kkkk kkkk kkkk kkkk kkkk kkkk rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk 0001 06rr 06rr 06rr 06rr 07rr 07rr 07rr 07rr 0xxx 0xxx 0xxx 0xxx 1kkk 1kkk 18kk 19kk 1Akk 1Bkk 1Ckk 1Dkk 1E01 1E8k 1Fkk RRCA R RRC R RLCA R RLC R SWAPA R SWAP R JZA R JZ R BC R,b BS R,b JBC R,b JBS R,b CALL k JMP k MOV A,k OR A,k AND A,k XOR A,k RETL k SUB A,k INT PAGE k ADD A,k R(n) A(n-1) R(0) C, C A(7) R(n) R(n-1) R(0) C, C R(7) R(n) A(n+1) R(7) C, C A(0) R(n) R(n+1) R(7) C, C R(0) R(0-3) A(4-7) R(4-7) A(0-3) R(0-3) R(4-7) R+1 A, skip if zero R+1 R, skip if zero 0 R(b) 1 R(b) if R(b)=0, skip if R(b)=1, skip PC+1 [SP] (Page, k) PC (Page, k) PC kA AkA A& k A AkA k A, [Top of Stack] PC k-A A PC+1 [SP] 001H PC K->R5(4:0) k+A A C C C C None None None None None None None None None None None Z Z Z None Z,C,DC None None Z,C,DC 1 1 1 1 1 1 2 if skip 2 if skip 1 1 2 if skip 2 if skip 2 2 1 1 1 1 2 1 1 1 1 1 1101 kkkk 1 1110 0000 1 1110 1kkk kkkk 1 1111 kkkk kkkk ** 1 Instruction cycle = 2 main CLK __________________________________________________________________________________________________________________________________________________________________ * This specification is subject to change without notice. 53 2004/8/19 (V1.6) EM78P813 8-bit OTP Micro-controller VII.9 CODE Option Register The controller has one CODE option register which is not part of the normal program memory. The option bits cannot be accessed during normal program execution. CODE Option Register1 ( Program ROM) 7 6 5 4 3 2 1 0 CWMODE /DED /PTB Bit 0(/PTB) : Program ROM data protect bit. 0/1 protect / unprotect When user clear this bit to 0, another person will unable read the originally program code from program ROM. Bit 1(/DED) : enable/disable DED function. 0 enable DED function 1 disable DED function Bit 2(CWMODE) : CAS tone (2130 Hz plus 2750 Hz ) accepted frequency range select. 0 2% Call waiting accepted frequency range deviation.(Application for China protocol : 1.5% ) 1.2% Call waiting accepted frequency range deviation.(Application for Europe and USA protocol : 0.5% ) 1 CODE Option Register2 ( Data ROM) 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 /DTB Bit 0(PTB) : Data ROM data protect bit. 0/1 protect / unprotect When user clear this bit to 0, another person will unable read the originally program code from data ROM. Bit 1~Bit 7 : Unused PAD Option /POVD(power on voltage detect) reset can be enabled/disabled by PAD Option. This POVD pad is not shown on the pin assignment. Internally or externally connecting this pad to GND/VDD to enable/disable /POVD reset. /POVD 2.2V /POVD reset voltage 2.2V Power on reset voltage Sleep mode current (VDD=5V) 1 No Yes (2.2V) 1uA 0 Yes (2.2V) No 15uA __________________________________________________________________________________________________________________________________________________________________ * This specification is subject to change without notice. 54 2004/8/19 (V1.6) EM78P813 8-bit OTP Micro-controller VII.10 CALL WAITING Function Description TIP DATA RING FSK demodulator /CD GAIN CWTIP + Filter Voltage reference Detection block CAS Vdd/2 Fig.33 Call Waiting Block Diagram Call Waiting service works by alerting a customer engaged in a telephone call to a new incoming call. This way the customer can still receive important calls while engaged in a current call. The CALL WAITING DECODER can detect CAS(Call-Waiting Alerting Signal 2130Hz plus 2750Hz) and generate a valid signal on the data pins. The call waiting decoder is designed to support the Caller Number Deliver feature, which is offered by regional Bell Operating Companies. In a typical application, after enabling CW circuit (by R5 page3 bit3 & bit4 ) this IC receives Tip and Ring signals from twisted pairs. The signals as inputs of pre-amplifier, and the amplifier sends input signal to a band pass filter. Once the signal is filtered, the Detection block decodes the information and sends it to RE page2 bit7 . The output data made available at RE CAS bit. The data is CAS signals. The CAS is normal high. When this IC detects 2130Hz and 2750Hz frequency, then CAS pin goes to low. __________________________________________________________________________________________________________________________________________________________________ * This specification is subject to change without notice. 55 2004/8/19 (V1.6) EM78P813 8-bit OTP Micro-controller VII.11 Differential Energy Detector (DED) EGIN1 EGIN2 DED DEDD DEDPWR DEDTHD EGCLK Fig.34 DED Block diagram The Differential Energy Detector is differential input level and zero crossing detector named as DED. It can detect any incoming AC signal above its threshold level and output corresponding zero-crossing frequency pulse. For this energy detector, the user can set it's minimum detection threshold level at -35dBm or -45dBm by DEDTHD bit. All the minimum detection value can be achieved under input capacitor more than 4700pF and input resistor around 100k ohms. The energy detector has power control by IOCE PAGE1 bit 1 (DEDPWR). Register bits of Energy Detector : Register bits Descriptions RE PAGE0 bit 3 (DED) DED : Interrupt flag of DED output data RE PAGE1 bit 7 (DEDD) DEDD : Output data of DED IOCE PAGE1 EDGE : edge control of DED output data Bit 5 (EDGE) 1/0 => Falling edge trig. / Rising edge and Falling edge trig. IOCE PAGE1 WUEDD : Wake-up control of DED output data Bit 4 (WUEDD) 1/0 => enable/disable IOCE PAGE1 DED : Interrupt mask of DED output data Bit 6 (DED) 1/0 enable/disable interrupt of DED output data IOCE PAGE1 DEDTHD : Minimum detection threshold of DED Bit 0 (DEDTHD) 0/1 -45dBm/-35dBm IOCE PAGE1 DEDPWR : Power control of DED Bit 1 (DEDPWR) 0/1 power off/power on IOCE PAGE1 DEDCLK : operating clock of DED Bit 2 (DEDCLK) 0 : low frequency clock 1 : high frequency clock __________________________________________________________________________________________________________________________________________________________________ * This specification is subject to change without notice. 56 2004/8/19 (V1.6) EM78P813 8-bit OTP Micro-controller VIII. Absolute Operation Maximum Ratings RATING DC SUPPLY VOLTAGE INPUT VOLTAGE OPERATING TEMPERATURE RANGE SYMBOL VDD Vin Ta Min -0.3 VDD-0.5 0 Typ VDD 25 Max 6 VDD+0.5 70 Unit V V J IX. DC Electrical Characteristic (Operation current consumption for Analog circuit) Parameter Symbol Condition Min Operation current for FSK I_FSK VDD=5V, CID power on VDD=3V, CID power on Operation current for CW I_CW VDD=5V, CID power on VDD=5V, CID power on Operation current for DTMF I_DR VDD=3V, DTMFr power on Receiver VDD=3V, DTMFr power on Operation current for TONE I_DTMF VDD=5V, DTMF power on generator VDD=3V, DTMF power on Current DA output current I_DA VDD=5V, CDA power on VDD=3V, CDA power on Operation current for OP I_OP VDD=5V, PT power on VDD=3V, PT power on Operation current for I_CMP VDD=5V, PT power on Comparator VDD=3V, PT power on (Ta=25C, VDD=5V5%, VSS=0V) Parameter Symbol Input Leakage Current for IIL1 input pins Input Leakage Current for IIL2 bi-directional pins Input High Voltage VIH Input Low Voltage VIL Input high threshold Voltage VIHT Input low threshold Voltage VILT Clock Input High Voltage VIHX Clock Input Low Voltage VILX Output High Voltage VOH1 (port 8,9,B,C,D) (port6,7,D) Output Low Voltage VOL1 (port 8,9,B,C,D) (port6,7) Pull-high current IPH Power down current (SLEEP mode) ISB1 Typ Max Unit 2.5 4 mA 2.0 3.5 2.5 4 mA 2.0 3.5 2.5 4.0 mA 2.0 3.5 0.9 1.2 mA 0.5 0.8 2.5 4 mA 2.0 3.5 0.17 mA 0.1 0.15 0.3 mA 0.13 0.2 Condition VIN = VDD, VSS VIN = VDD, VSS Min Typ Max Unit 1 A 1 A V V V V V V V V V V A A 2.0 0.8 /RESET, TCC, RDET1 /RESET, TCC,RDET1 OSCI OSCI IOH = -6mA IOH = -10.0mA IOL = 6mA IOL = 10.0mA Pull-high active input pin at VSS All input and I/O pin at VDD, output pin floating, 2.0 0.8 1.8 1.2 2.0 2.0 2.4 2.4 0.4 0.4 -15 4 -10 1 __________________________________________________________________________________________________________________________________________________________________ * This specification is subject to change without notice. 57 2004/8/19 (V1.6) EM78P813 8-bit OTP Micro-controller WDT disabled CLK=32.768KHz,All analog circuit disable , All input and I/O pin at VDD, output pin floating, WDT disabled, LCD disable /RESET=High, PLL enable CLK=3.579MHz, output pin floating, LCD disable, all analog circuit disable 0.5 Low clock current (GREEN mode) ISB2 35 50 A Operating supply current (NORMAL mode) ICC 2.8 3.5 mA Tone generator voltage reference Vref2 0.7 VDD Differential Energy Detector (DED) (Ta=25C, VDD=5.0V5%, VSS=0V) Symbol Parameter Condition Min EGIN1 Operating current for SED SEDCLK bit = 0 EGIN2 Operating current for SED SEDCLK bit = 0 Typ 20 20 Max Unit 25 A 25 A Embedded LCD driver Symbol Ron Parameter LCD driver ON resistance LCD frame frequency Condition LCD function enable 1/24 duty 1/16 , 1/32 duty Dynamic current consumption Charge pump x 2 , no load Voltage converter output LCD driver current Charge pump x 2 , no load Weak mode Normal mode Strong mode Double strong mode Min Typ 2 88 64 60 97 75 150 300 600 Max Unit 4 k Hz Hz 65 A % f FM I DCC VOUT I driver 95 A A A A X. AC Electrical Characteristic CPU instruction timing (Ta=25C, VDD=5V, VSS=0V) Parameter Symbol Condition Input CLK duty cycle Dclk Instruction cycle time Tins 32.768kHz 3.579MHz Device delay hold time Tdrh TCC input period Ttcc Note 1 Watchdog timer period Twdt Ta = 25C Note 1: N= selected prescaler ratio. Min 45 Typ 50 60 550 16 16 Max 55 Unit % us ns ms ns ms (Tins+20)/N __________________________________________________________________________________________________________________________________________________________________ * This specification is subject to change without notice. 58 2004/8/19 (V1.6) EM78P813 8-bit OTP Micro-controller FSK AC Characteristic (Vdd=5V,Ta=+25C) CHARACTERISTIC FSK sensitivity Low Level Sensitivity Tip & Ring @SNR 20dB High Level Sensitivity Tip & Ring @SNR 20dB Signal Reject FSK twist Positive Twist (High Level) Positive Twist (Low Level) Negative Twist (High Level) Negative Twist (Low Level) Min -40 Typ -48 0 -51 Max Unit dBm dBm dBm dB dB dB dB +10 +10 -6 -6 DTMF (DTMF receiver) AC Characteristic (Vdd=5V,Ta=+25C) CHARACTERISTIC DTMF receiver Low Level Signal Sensitivity High Level Signal Sensitivity Low Tone Frequency High Tone Frequency DTMF receiver noise endurance Signal to noise ratio Min Typ -36 0 2 2 15 Max Unit dBm dBm % % dB TONE generators for AC Characteristic (Vdd=5V,Ta=+25C) CHARACTERISTIC Min Typ Tone1/Tone2 signal strength (root mean square voltage) Tone1 signal strength V1rms (ps1) 130 155 Tone2 signal strength V2rms (ps1) 1.259V1rms Max Unit 180 o o V V Tone twist (Tone1 - Tone2) twist -2 dB Tone frequency deviation Frequency deviation 1 % (ps1) : V1rms and V2rms has 2dB difference. It means 20log(V2rms/V1rms) = 20log1.259 = 2 (dB) DED AC Characteristic (Vdd=+5.0V,Ta=+25J ) CHARACTERISTIC MIN TYP MAX UNIT Input sensitivity TIP and RING for DED, DEDTHD bit=0 -45 -dBm Input sensitivity TIP and RING for DED, DEDTHD bit=1 -35 -dBm Timing characteristic (Vdd=5V,Ta=+25C) Description Oscillator timing characteristic OSC start up FSK timing characteristic Carrier detect low Carrier detect low to data valid Power up to FSK(setup time) End of FSK to Carrier Detect high Symbol 32.768kHz Tosc 3.579MHz PLL Tcdl Tcdv Tsup Tcdh ---Min Typ Max Unit 1500 ms 10 us 14 20 20 4 ms ns ms ms 5 10 10 15 -- __________________________________________________________________________________________________________________________________________________________________ * This specification is subject to change without notice. 59 2004/8/19 (V1.6) EM78P813 8-bit OTP Micro-controller CW timing characteristic CAS input signal length Tcasi 80 (2130 ,2750 Hz @ -20dBm ) Call waiting data detect delay time Tcwd 42 Call waiting data release time Tcwr 26 DTMF receiver timing characteristic Tone Present Detection Time Tdp (ps1) the guard-times for tone-present Tgtp 30 (C=0.1uF, R=300K) the guard-times for tone-absent Tgta 30 (C=0.1uF, R=300K) Propagation Delay (St to Q) Tpq 8 Tone Absent Detection Time Tda (ps2) SPI timing characteristic (CPU clock 3.58MHz and Fsco = 3.58Mhz /2) /SS set-up time Tcss 560 /SS hold time Tcsh 250 SCLK high time Thi 250 SCLK low time Tlo 250 SCLK rising time Tr 15 SCLK falling time Tf 15 SDI set-up time to the reading edge of SCLK Tisu 25 SDI hold time to the reading edge of SCLK Tihd 25 SDO disable time Tdis (ps1) : Controlled by software (ps2) : Controlled by RC circuit. Data ROM access timing characteristic Symbol Description Condition Min Typ Tdiea Delay from Phase 3 end to Cl=100pF INSEND active Tdiei Delay from Phase 4 end to Cl=100pF INSEND inactive Tiew INSEND pulse width 30 Tdca Delay from Phase 4 end to C1=100pF CA Bus valid Tacc ROM data access time 100 Tcds ROM data setup time 20 Tcdh ROM data hold time 20 Tdca-1 Delay time of CA-1 C1=100pF ms ms ms ms mS us ms ns ns ns ns ns ns ns ns 30 30 560 Max 30 30 Unit ns ns ns ns ns ns ns ns 30 30 __________________________________________________________________________________________________________________________________________________________________ * This specification is subject to change without notice. 60 2004/8/19 (V1.6) EM78P813 8-bit OTP Micro-controller XI. Timing Diagrams ins Fig.38 AC timing __________________________________________________________________________________________________________________________________________________________________ * This specification is subject to change without notice. 61 2004/8/19 (V1.6) EM78P813 8-bit OTP Micro-controller FIRST RING 2 SECONDS TIP/RING 0.5 SEC 0.5 SEC SECOND RING 2SECONDS / TRIG Tcdl /CD Tdoc DATA (internal clock) Tsup /358E DATA Tcdh 3.579 M Hz Fig.39 FSK timing diagram p lu g on in hook C AS Tc a s i events normal in use Tc w d CAS Tc w r CW PW R power off power on Fig.40 Call waiting timing diagram __________________________________________________________________________________________________________________________________________________________________ * This specification is subject to change without notice. 62 2004/8/19 (V1.6) EM78P813 8-bit OTP Micro-controller TONE Tdp 5~20mS by S/W Tgtp 30mS Typ. ST/GT TONE Tgta 30mS Typ. EST Vtst 1/2 VDD Tpq 8 uS Typ. Q4..Q1 STD LINE_ENG Fig.41 DTMF receiver timing diagram __________________________________________________________________________________________________________________________________________________________________ * This specification is subject to change without notice. 63 2004/8/19 (V1.6) EM78P813 8-bit OTP Micro-controller XII Application Circuit LCD pannel 32x98 pixels VDD SEGMENT CA 4.7u CB VDD 27p 27p 0.1u VDD,AVDD,LVDD XIN 32.768k XOUT PLLC AVSS,GND EGIN1 4700p 4700p 47K EGIN1 47K TIP 4700p 4700p 47K RING 47K CWGS CWIN COMMON STGT EST VOUT 1u VC1 VC2 VC3 VC4 TIP LINE RING EM78P813 VC5 1u 1u 1u 1u 1u VREF 1u 47p 150K 39K 4700p Line Interface Speech Network Fig.43 Internal LCD driver application circuit __________________________________________________________________________________________________________________________________________________________________ * This specification is subject to change without notice. 64 2004/8/19 (V1.6) EM78P813 8-bit OTP Micro-controller LCD pannel 65x264 pixels COMMON SEGMENT COMMON FR CL /DOF V0 V1 V2 V3 V4 SEGMENT FR CL /DOF LCD driver V0 EM9L8580(master) V1 V2 ( support max 65x132 pixels) V3 V4 P/S M/S D0..D7 /RES CLK A0 /RD /WR /CS1 LCD driver EM9L8580(slave) ( support max 65x132 pixels) /RD /WR /CS1 /RES P/S M/S VDD D0..D7 CLK A0 VDD 8 XOUT Reset PB7~PB0 VDD,AVDD VDD XIN 27p 27p 0.1u 32.768k XOUT PLLC AVSS,GND TIP 4700p 47K RING 47K TIP 4700p 47K RING 47K CWGS CWIN PC5 PC4 TIP LINE RING 4700p EM 78P813 PC7 PC6 PC3 SEG65 SEG52 SEG51 SEG50 P70 STGT EST Key matrix P71 P72 P73 VDD 4700p SEG34 ~ SEG65 (Share with interface) EXTERNAL Memory 47p 150K 39K 4700p Line Interface Speech Network Fig.44 External multi-chip LCD driver application circuit __________________________________________________________________________________________________________________________________________________________________ * This specification is subject to change without notice. 65 2004/8/19 (V1.6) |
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